Power efficient multiplexer
First Claim
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1. A power efficient multiplexer comprising:
- a latch circuit configured to output at least one bit and a complement of said at least one bit;
a transmission gate structure configured to selectively pass one of a plurality of input signals based at least in part on said at least one bit and said complement outputted by said latch circuit; and
a stacked inverter circuit configured to invert, independently of said at least one bit and said complement and a state of a clock signal, said one of said plurality of input signals at an output node.
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Abstract
A power efficient multiplexer. In accordance with a first embodiment of the present invention, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.
151 Citations
19 Claims
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1. A power efficient multiplexer comprising:
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a latch circuit configured to output at least one bit and a complement of said at least one bit; a transmission gate structure configured to selectively pass one of a plurality of input signals based at least in part on said at least one bit and said complement outputted by said latch circuit; and a stacked inverter circuit configured to invert, independently of said at least one bit and said complement and a state of a clock signal, said one of said plurality of input signals at an output node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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accessing a plurality of electronic signals; outputting a bit value and a complement of said bit value from a latch circuit; configuring a plurality of transmission gates to select one electronic signal from said plurality of electronic signals by using said bit value and said complement outputted by said latch circuit; and inverting, independently of said bit value and said complement and a state of a clock signal, said one electronic signal by utilizing a stacked inverter circuit. - View Dependent Claims (10, 11, 12, 13, 14)
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15. An electronic circuit comprising:
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a latch circuit configured to output at least one bit and a complement of said at least one bit; a stacked inverter circuit configured to operate independently of a state of a clock signal, wherein said stacked inverter circuit comprises; at least two devices of a first type coupled in series, and at least two devices of a second type coupled in series and coupled in series to said at least two devices of said first type, wherein said second type is opposite to said first type; a first transmission gate including a first conductance terminal configured to receive a first electronic signal and a second conductance terminal coupled to an input of said stacked inverter circuit; and a second transmission gate including a first conductance terminal configured to receive a second electronic signal and a second conductance terminal coupled to said input of said stacked inverter circuit, wherein said first and second transmission gates pass one of said first and second electronic signals based at least in part on said at least one bit and said complement outputted by said latch circuit, and wherein said stacked inverter circuit is configured to operate independently of said at least one bit and said complement outputted by said latch circuit. - View Dependent Claims (16, 17, 18, 19)
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Specification