Programmable dual phase-locked loop clock signal generator and conditioner

• US 8,102,196 B1
• Filed: 04/14/2010
• Issued: 01/24/2012
• Est. Priority Date: 06/27/2008
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Zhang, Benyong
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): HOUSTON, ADAM D
• Application Number:
  US12/759,987
• Time in Patent Office: 650 Days
• Field of Search: 327/156, 327/147
• US Class Current: 327/156
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03L 7/235 Nested phase locked loops

Abstract

A clock signal generator and conditioner in which dual integrated phase-locked loop (PLL) circuits use an off-chip frequency-pullable crystal resonator or voltage-controlled oscillator (VCO) module and an on-chip VCO with intra-PLL frequency doubling to provide a clock signal with reduced in-band phase noise and RMS jitter. As desired, synchronization between the input and output clocks can also be provided.

Claims

1. An apparatus including integrated clock signal generator circuitry, comprising:

a first electrode to convey an off-chip control signal for off-chip voltage-controlled oscillator (VCO) circuitry;

a second electrode to convey from said off-chip VCO circuitry an off-chip VCO signal having a first frequency related to said off-chip control signal;

first phase detection circuitry coupled to said first and second electrodes and responsive to an input reference signal and a phase lock loop (PLL) signal by providing said off-chip control signal;

frequency alteration circuitry coupled to said second electrode and responsive to said off-chip VCO signal by providing an intermediate signal having a second frequency related to said first frequency; and

PLL circuitry coupled to said frequency alteration circuitry and responsive to said intermediate signal by providing said PLL signal, wherein said PLL signal has a third frequency related to said second frequency and is synchronized with said input reference signal.

2. The apparatus of claim 1, wherein said first phase detection circuitry comprises:

phase-frequency detection circuitry responsive to said input reference signal and a feedback signal by providing said off-chip control signal; and

frequency division circuitry responsive to said PLL signal by providing said feedback signal.

3. The apparatus of claim 1, wherein:

said frequency alteration circuitry comprises controllable circuitry responsive to said off-chip VCO signal and one or more control signals by providing said intermediate signal; and

said second frequency is selectively related to said first frequency by one of a divisor and a multiplicand.

4. The apparatus of claim 1, wherein said frequency alteration circuitry comprises:

frequency division circuitry responsive to at least said off-chip VCO signal by providing a frequency-divided signal having a fourth frequency related to said third frequency by a divisor;

signal delay circuitry responsive to said off-chip VCO signal by providing a delayed signal having said third frequency;

signal comparison circuitry coupled to said signal delay circuitry and responsive to said off-chip VCO signal and delayed signal by providing a resultant signal having a fifth frequency related to said third frequency by a multiplicand; and

signal selection circuitry coupled to said frequency division circuitry and said signal comparison circuitry, and responsive to one or more control signals by providing one of said delayed signal and resultant signal as said intermediate signal.

5. The apparatus of claim 1, wherein said PLL circuitry comprises:

second phase detection circuitry responsive to said intermediate signal and an on-chip VCO signal by providing an on-chip control signal; and

on-chip VCO circuitry coupled to said second phase detection circuitry and responsive to said on-chip control signal by providing said on-chip VCO signal.

6. The apparatus of claim 5, wherein said PLL circuitry further comprises frequency division circuitry responsive to said on-chip VCO signal by providing said PLL signal.

7. The apparatus of claim 5, wherein said second phase detection circuitry comprises:

phase-frequency detection circuitry responsive to said intermediate signal and a feedback signal by providing said on-chip control signal; and

frequency division circuitry responsive to said on-chip VCO signal by providing said feedback signal.

8. The apparatus of claim 5, wherein said on-chip VCO circuitry comprises a resonant tank circuit.

9. The apparatus of claim 8, wherein said resonant tank circuit comprises integrated inductive circuitry and integrated capacitive circuitry.

10. An apparatus including integrated clock signal generator circuitry, comprising:

first phase detector means for receiving an input reference signal and a phase lock loop (PLL) signal and in response thereto providing an off-chip control signal for off-chip voltage-controlled oscillator (VCO) circuitry;

frequency alteration means for receiving an off-chip VCO signal from said off-chip VCO circuitry and in response thereto providing an intermediate signal, wherein said off-chip VCO signal has a first frequency related to said off-chip control signal and said intermediate signal has a second frequency related to said first frequency; and

PLL means for receiving said intermediate signal and in response thereto providing said PLL signal, wherein said PLL signal has a third frequency related to said second frequency and is synchronized with said input reference signal.