Dynamically controlled power reduction method and circuit for a graphics processor

• US 8,102,398 B2
• Filed: 03/03/2006
• Issued: 01/24/2012
• Est. Priority Date: 03/03/2006
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Bajic, Ljubisa, Fry, James
• Primary Examiner(s): WASHBURN, DANIEL C
• Application Number:
  US11/366,619
• Publication Number:
  US 20070206018A1
• Time in Patent Office: 2,153 Days
• Field of Search: 345/503, 713/320
• US Class Current: 345/503
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A graphics processor may be operated in a reduced power mode to render frames at rate equal to or less than the rate at which frames are presented on an interconnected display. Graphics processor clock speeds are controlled to reduce the time during which the graphics processor is idle between rendering frames. The graphics processor clock speed may thus be slowed without impacting the quality of rendered images. At the same time the voltage applied to power the graphics processor may be reduced. Optionally, a back bias voltage may further be applied to the processor substrate to reduce power consumption. Clock speed and voltage levels may be adjusted using closed-loop control.

Claims

1. A method of operating a graphics accelerator comprising:

operating a graphics processor to render frames in frame buffer memory at a frame rendering rate that exceeds a frame refresh rate of a display interconnected with said graphics processor;

sampling said frame buffer memory at said frame refresh rate to display graphics on said display at said frame refresh rate, wherein at said frame rendering rate, the number of frames rendered exceeds the number of frames displayed on said display;

in response to detecting a desired reduced power mode, adjusting under software control, said frame rendering rate of said graphics processor to an adjusted frame rendering rate equal to or less than said frame refresh rate, and rendering graphics to be displayed on said display in said frame buffer memory, at said adjusted frame rendering rate, without adjusting said frame refresh rate;

controlling said frame rendering rate of said graphics processor so that idle time of said graphics processor between rendering frames at said adjusted frame rendering rate is controlled.

2. The method of claim 1, wherein said controlling comprises controlling operation of said graphics processor so that idle time of said graphics processor reaches a pre-programmed value.

3. The method of claim 2, wherein said pre-programmed value is less than ½

of a period of said frame refresh rate.

4. The method of claim 2, wherein said pre-programmed value is less than ¼

of a period of said frame refresh rate.

5. The method of claim 2, wherein said pre-programmed value is less than 1/10 of a period of said frame refresh rate.

6. The method of claim 1, wherein said controlling further comprises adjusting a clock frequency of an operating clock of said graphics processor.

7. The method of claim 6, wherein said operating clock is an operating clock for a graphics engine of said graphics processor.

8. The method of claim 7, wherein said controlling further comprises adjusting a supply voltage to said graphics engine of said graphics processor.

9. The method of claim 8, wherein adjusting said supply voltage comprises using a look-up table to determine a voltage in dependence on said clock frequency.

10. The method of claim 7, further comprising adjusting a bias voltage applied to a substrate of said graphics processor.

11. The method of claim 10, wherein adjusting said bias voltage comprises using a look-up table to determine a back bias voltage in dependence on at least one of said clock frequency and said supply voltage.

12. The method of claim 6, further comprising generating a signal indicative of said graphics processor idling, and wherein said controlling comprises generating an error signal representative of the desired idle time, and the actual idle time of said graphics processor.

13. The method of claim 12, further comprising filtering said signal indicative of said graphics processor idling to generate a control signal for controlling said operating clock of said graphics processor.

14. The method of claim 13, wherein said filtering comprises filtering said signal indicative of said processor idling signal using an N-tap FIR filter.

15. The method of claim 1, wherein said adjusting under software control a frame rendering rate of a graphics processor to an adjusted frame rendering rate comprises waiting for a vertical blank signal before rendering a next frame.

16. A graphics accelerator comprising:

a graphics engine for rendering graphical images to be displayed on a display;

an adjustable clock source, for providing an operating clock signal to said graphics engine;

frame buffer memory;

a display interface for sampling said frame buffer memory at a frame refresh rate, to display graphics on said display at a frame refresh rate;

said graphics engine operable under software control to render frames at a first frame rendering rate that exceeds said frame refresh rate to said frame buffer memory, and, in response to detecting a desired reduced power mode, at a reduced second frame rendering rate equal to or less than said frame refresh rate, without adjusting said adjustable clock source and without adjusting said frame refresh rate;

a controller in communication with said graphics engine and said adjustable clock, to control a frequency of said adjustable clock source so that said graphics engine remains idle for a defined time between frames as said graphics engine renders frames at said reduced second frame rendering rate.

17. The graphics accelerator of claim 16, further comprising a controllable voltage supply to supply an operating voltage to said graphics engine, and wherein said controller is further in communication with said controllable voltage supply to adjust said operating voltage in dependence on said frequency of said adjustable clock source.

18. The graphics accelerator of claim 17, further comprising a second controllable voltage supply to supply a back bias voltage to a substrate of said graphics engine, and wherein said controller is further in communication with said controllable voltage supply to adjust said back bias voltage in dependence on at least one of said frequency of said adjustable clock source and said operating voltage.

19. The graphics accelerator of claim 18, wherein said controller comprises a multi-tap FIR filter to filter idle time over multiple frames.

20. The graphics accelerator of claim 17, further comprising a look-up table used to determine said operating voltage.

21. The graphics accelerator of claim 18, further comprising a look-up table used to determine said back bias voltage.

22. The graphics accelerator of claim 18, wherein said controller adjusts said clock in increments, and wherein said increments vary in dependence on said error.

23. A computing device comprising the graphics accelerator of claim 16.

24. A computing device comprising:

frame buffer memory;

means for rendering graphics frames to said frame buffer memory at a frame generation rate;

an adjustable clock source, for providing an operating clock signal to said graphics engine;

means for sampling said frame buffer memory at a frame refresh rate, to display graphics on said display at said frame refresh rate;

means for, in response to detecting a reduced power condition, limiting said frame generation rate from a rate that exceeds said frame refresh rate to an adjusted frame generation rate equal to or less than said frame refresh rate, without adjusting said adjustable clock source and without adjusting said frame refresh rate;

means for controlling operation of said adjustable clock source so that idle time of said means for rendering between rendered frames at said adjusted frame rate is reduced.