Distortion resistant array substrate and touch-sensitive display panel having the same

• US 8,102,496 B2
• Filed: 12/09/2009
• Issued: 01/24/2012
• Est. Priority Date: 07/25/2006
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Gyu
• Primary Examiner(s): Robinson, Mark
• Assistant Examiner(s): INADOMI, MICHAEL J
• Application Number:
  US12/634,607
• Publication Number:
  US 20100085500A1
• Time in Patent Office: 776 Days
• Field of Search: 349/141, 349/39
• US Class Current: 349/141
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display

Abstract

An array substrate includes a plurality of gate lines, a plurality of data lines, a plurality of thin-film transistors, a plurality of pixel electrodes, a plurality of common voltage lines and a plurality of common electrodes. The gate lines extend in a first direction. The data lines extend in a second direction substantially perpendicular to the first direction. The thin-film transistor is electrically connected to the gate line and the data line. The pixel electrode is formed in each of pixels defined by the gate lines and the data lines. The common electrode is electrically connected to the common voltage line. The horizontal alignment of the liquid crystal molecules is not changed by externally applied vertical touch pressure so that display quality is improved.

Claims

1. An array substrate comprising:

a plurality of gate lines extending in a first direction;

a plurality of data lines extending in a second direction substantially perpendicular to the first direction, the intersecting directions of the data lines and gate lines defining a plurality of pixels;

a plurality of thin-film transistors electrically connected to the gate lines and the data lines;

a pixel electrode electrically connected to a thin-film transistor;

a common voltage line extending in the second direction substantially parallel with the data lines;

an insulation layer formed on the common voltage line;

a common electrode formed in each of the pixels, electrically insulated from the pixel electrode, and electrically connected to the common voltage line, and

a horizontal connection electrode disposed between adjacent common electrodes and electrically connecting the adjacent common electrodes to each other,

wherein the common electrode is formed from a layer substantially the same as the pixel electrode on the insulation layer,

wherein the horizontal connection electrode is formed from the layer substantially the same as the common electrode.

2. The array substrate of claim 1, wherein the pixel electrode and the common electrode comprise a transparent conductive material.

3. The array substrate of claim 2, wherein the pixel electrode comprises:

a main pixel electrode that extends in the first direction, and is adjacent to one of the gate lines; and

a plurality of sub pixel electrodes protruding from the main pixel electrode toward a consecutive one of the gate lines, the sub pixel electrodes being arranged in the first direction.

4. The array substrate of claim 3, wherein the common electrode comprises:

a main common electrode that extends in the first direction, and is adjacent to a consecutive one of the gate lines; and

a plurality of sub common electrodes protruding from the main common electrode toward the main pixel electrode, the sub common electrodes being arranged in the first direction.

5. The array substrate of claim 4, wherein the sub pixel electrodes are symmetric with respect to a central line of a pixel, which is substantially parallel with the second direction, and the sub common electrodes are symmetric with respect to the central line.

6. The array substrate of claim 5, wherein the sub pixel electrodes comprise:

a first sub pixel electrode that is adjacent to a first side of the central line, and is tilted at a predetermined angle to the second direction; and

a second sub pixel electrode that is adjacent to a second side of the central line, which is opposite to the first side, and is tilted at a predetermined angle to the second direction so that the first and second sub pixel electrodes are symmetric with respect to the central line, and

the sub common electrodes comprise;

a first sub common electrode that is adjacent to a first side of the central line, and is substantially parallel with the first sub pixel electrode; and

a second sub common electrode that is adjacent to a second side of the central line, which is opposite to the first side, and is substantially parallel with the second sub pixel electrode.

7. The array substrate of claim 4, wherein the common electrode is formed over the common voltage line and is electrically connected to the common voltage line through a contact hole formed through the insulation layer.

8. A display panel comprising:

an array substrate that comprises;

a plurality of gate lines extending in a first direction;

a plurality of data lines extending in a second direction substantially perpendicular to the first direction;

a plurality of thin-film transistors electrically connected to the gate line and the data line;

a pixel electrode electrically connected to each of the thin-film transistors;

a common voltage line extending in the second direction substantially parallel with the data line;

an insulation layer formed on the common voltage line;

a common electrode formed in each of the pixels electrically insulated from the pixel electrode and electrically connected to the common voltage line;

an opposite substrate facing the array substrate;

a liquid crystal layer interposed between the array substrate and the opposite substrate and having liquid crystal molecules, and

a horizontal connection electrode disposed between adjacent common electrodes and electrically connecting the adjacent common electrodes to each other,

wherein the common electrode is formed from a layer substantially the same as the pixel electrode on the insulation layer, and

wherein the horizontal connection electrode is formed from the layer substantially the same as the common electrode.

9. The display panel of claim 8, wherein the liquid crystal molecules of the liquid crystal layer are aligned substantially parallel with a surface of the array substrate, and are rotated by an electric field formed by the pixel electrode and the common electrode by a predetermined angle while being substantially parallel with the surface of the array substrate.