Nonvolatile memory device containing carbon or nitrogen doped diode

• US 8,102,694 B2
• Filed: 06/25/2007
• Issued: 01/24/2012
• Est. Priority Date: 06/25/2007
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Herner, S. Brad, Clark, Mark H., Kumar, Tanmay
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US11/819,042
• Publication Number:
  US 20080316808A1
• Time in Patent Office: 1,674 Days
• Field of Search: 365/148, 365/158, 365/163, 365/171, 365/173, 365/230.06, 365/103, 365/105, 365/175, 257/155, 257/474, 257/E21.108, 438/482
• US Class Current: 365/148
• CPC Class Codes: G11C 11/36 using diodes, e.g. as threshold elements , i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)

Abstract

A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration.

Claims

1. A nonvolatile memory device, comprising at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration,

wherein the concentration of carbon in the silicon, germanium or silicon-germanium diode is lower than 1×

10²¹ cm<sup>−

3</sup> and the concentration of nitrogen in the silicon, germanium or silicon-germanium diode is lower than 1×

10²¹ cm<sup>−

3</sup>; and

wherein the diode has a leakage current of less than 4×

10<sup>−

10</sup> A at −

5.5 V in the high resistivity, reset state.

2. The device of claim 1, further comprising a first electrode and a second electrode electrically contacting the at least one nonvolatile memory cell.

3. The device of claim 2, wherein in use, the diode acts as a read/write element of the nonvolatile memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

4. The device of claim 2, wherein the nonvolatile memory cell consists essentially of the diode and first and second electrodes electrically contacting the diode.

5. The device of claim 2, wherein:

the nonvolatile memory cell consists essentially of first and second electrodes, the diode and an antifuse; and

the diode and the antifuse are located in series between the first and the second electrodes.

6. The device of claim 1, wherein the diode is doped with carbon in a concentration of at least 1×

10¹⁷ cm<sup>−

3</sup>.

7. The device of claim 1, wherein the diode is doped with nitrogen in a concentration of at least 1×

10¹⁷ cm<sup>−

3</sup>.

8. The device of claim 1, wherein the diode is doped with carbon and nitrogen in a combined concentration of at least 1×

10¹⁷ cm<sup>−

3</sup>.

9. The device of claim 1, wherein the diode comprises a p-i-n diode and at least an intrinsic region of the diode is doped with the at least one of carbon or nitrogen.

10. The device of claim 1, wherein the diode comprises a polycrystalline silicon, germanium or silicon-germanium p-i-n pillar diode having a substantially cylindrical shape.

11. The device of claim 1, wherein:

the nonvolatile memory cell comprises a read/write memory cell; and

the diode which acts as a read/write element of the nonvolatile memory cell.

12. The device of claim 11, wherein the nonvolatile memory cell comprises a rewritable memory cell.

13. The device of claim 12, wherein:

the diode in an initial high resistivity, unprogrammed state is adapted to be placed in a low resistivity, programmed state by an application of a forward bias to the diode;

the diode in the programmed, low resistivity state is adapted to be placed in the high resistivity, reset state by an application of a reverse bias to the diode; and

the diode in the high resistivity, reset state is adapted to be returned to the low resistivity, programmed set state by an application of a forward bias to the diode.

14. The device of claim 1, wherein the carbon or nitrogen provide at least one of reduced power, increased bandwidth or improved temperature characteristics to the memory cell during read and program operations.

15. The device of claim 1, further comprising a monolithic, three dimensional array of nonvolatile memory cells located over the diode.

16. The device of claim 1, wherein a p-type region of the diode is doped with boron and an n-type region of the diode is doped with phosphorus.

17. A nonvolatile memory device, comprising:

at least one nonvolatile memory cell which comprises a silicon, germanium or silicon germanium p-i-n diode in which at least an intrinsic region and at least one of a p-type and a n-type regions are doped with at least one of nitrogen or carbon in a concentration greater than 1×

10¹⁷ cm<sup>−

3</sup>;

wherein the concentration of carbon in the silicon, germanium or silicon-germanium p-i-n diode is lower than 1×

10²¹ cm<sup>−

3</sup> and the concentration of nitrogen in the silicon, germanium or silicon-germanium p-i-n diode is lower than 1×

10²¹ cm<sup>−

3</sup>;

wherein the diode has a leakage current of less than 4×

10¹⁰ A at −

5.5 V in the high resistivity, reset state; and

a first electrode and a second electrode electrically contacting the at least one nonvolatile memory cell.

18. The device of claim 17, wherein in use, the diode acts as a read/write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

19. The device of claim 18, wherein the nonvolatile memory cell consists essentially of the diode and the first and the second electrodes electrically contacting the diode.

20. The device of claim 18, wherein:

the nonvolatile memory cell consists essentially of the first and the second electrodes, the diode and an antifuse; and

the diode and the antifuse are located in series between the first and the second electrodes.

21. The device of claim 18, wherein the nonvolatile memory cell comprises a rewritable memory cell.

22. The device of claim 17, wherein a p-type region of the diode is doped with boron and an n-type region of the diode is doped with phosphorus.