Structure and method for biasing phase change memory array for reliable writing
First Claim
1. In an integrated circuit comprising memory cells comprising phase change memory elements, a structure within the integrated circuit for writing to the memory cells comprising:
- a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current;
a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width; and
a bit line driver receiving the controlled current and an unselected bit line voltage, the bit line driver selecting between providing to a bit line the controlled current and the unselected bit line voltage in response to a driver control signal, the bit line providing the controlled current to at least one of the memory cells comprising phase change memory elements.
5 Assignments
0 Petitions
Accused Products
Abstract
A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.
220 Citations
30 Claims
-
1. In an integrated circuit comprising memory cells comprising phase change memory elements, a structure within the integrated circuit for writing to the memory cells comprising:
-
a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current; a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width; and a bit line driver receiving the controlled current and an unselected bit line voltage, the bit line driver selecting between providing to a bit line the controlled current and the unselected bit line voltage in response to a driver control signal, the bit line providing the controlled current to at least one of the memory cells comprising phase change memory elements. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. In an integrated circuit comprising memory cells comprising phase change memory elements, a structure for fast successive writing to the memory cells comprising:
-
a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current; a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width; a deselection control device for providing an unselected voltage to the output terminal at times not within the pulse width; and structure for connecting the output terminal to terminals of a plurality of the memory cells. - View Dependent Claims (16, 17, 18, 19)
-
-
20. An integrated circuit structure comprising:
a structure for writing to memory cells comprising phase change memory elements, the structure for writing comprising; a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current; a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width; and a plurality of memory cells for storing integrated circuit control information, each comprising a series combination of;
a phase change material and an antifuse.- View Dependent Claims (21, 22, 23)
-
24. An integrated circuit memory comprising:
-
a plurality of memory cells layers, each memory cell layer comprising; a layer of bit lines extending in a first direction; a layer of word lines extending in a second direction; and a layer of phase change memory cells, each phase change memory cell extending between one of the bit lines and one of the word lines; and structure for controlling current and pulse width for writing the phase change memory cells comprising; a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current; and a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width. - View Dependent Claims (25, 26, 27, 28, 29, 30)
-
Specification