System and method for setting access and modification for synchronous serial interface NAND

• US 8,102,710 B2
• Filed: 10/17/2007
• Issued: 01/24/2012
• Est. Priority Date: 10/17/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pekny, Theodore T., Tsai, Victor Y.
• Primary Examiner(s): Phan, Trong
• Application Number:
  US11/873,826
• Publication Number:
  US 20090103362A1
• Time in Patent Office: 1,560 Days
• Field of Search: 365/185.08, 365/185.11, 365/185.12, 365/185.17, 365/185.18, 365/185.29, 365/185.33, 365/233.1, 365/238.5, 365/240, 365/185.09, 711/157
• US Class Current: 365/185.08
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device. One embodiment generally includes sending an enable signal to a first memory circuit input, sending a clock signal to a second memory circuit input, sending a command signal synchronized to the clock signal to a third memory circuit input, sending a memory register address signal synchronized to the clock signal to the third memory circuit input, and sending a setting signal synchronized to the clock signal to the third memory circuit input.

Claims

1. A method of operating an SPI NAND flash memory device comprising:

sending an enable signal to a first NAND memory circuit input;

sending a clock signal to a second NAND memory circuit input;

sending a register write command signal to a third NAND memory circuit input, wherein the register write command signal is synchronized to the clock signal;

sending a memory register address signal to the third NAND memory circuit input, wherein the memory register address signal is synchronized to the clock signal; and

sending a data signal to the third NAND memory circuit input, wherein the data signal is synchronized to the clock signal.

2. The method of claim 1, wherein sending the memory register address signal to the third NAND memory circuit input immediately follows sending the register write command signal to the third NAND memory circuit input, and wherein sending the data signal to the third NAND memory circuit input immediately follows sending the memory register address signal to the third NAND memory circuit input.

3. The method of claim 1, wherein sending the register write command signal to the third NAND memory circuit input, sending the memory register address signal to the third NAND memory circuit input, and sending the data signal to the third NAND memory circuit input each comprises sending a one-byte signal.

4. The method of claim 1, wherein sending the register write command signal to the third NAND memory circuit input comprises sending a register write command of one byte to the third NAND memory circuit input.

5. The method of claim 4, wherein sending the register write command of one byte to the third NAND memory circuit input comprises sending a signal with a hexadecimal format of 1Fh to the third NAND memory circuit input.

6. A method of operating a NAND flash memory device comprising:

sending an enable signal to a first NAND flash input pin;

sending a master clock signal to a second NAND flash input pin;

at the start of a first rising clock edge of the master clock signal, sending a one-byte register read command to a third NAND flash input pin, wherein the one-byte register read command corresponds synchronously to the master clock signal;

immediately after sending the one-byte register read command to the third NAND flash input pin, sending a register address to the third NAND flash input pin, wherein the register address corresponds synchronously to the master clock signal; and

receiving output data from an output pin, wherein the output data corresponds synchronously to the master clock signal.

7. The method of claim 6, wherein sending the one-byte register read command to the third NAND flash input pin comprises sending a byte having a hexadecimal format of 0Fh to the third NAND flash input pin.

8. The method of claim 6, wherein receiving output data from an output pin immediately follows sending a register address to the third NAND flash input pin.

9. The method of claim 6, wherein sending the register address to the third NAND flash input pin comprises sending a one-byte signal corresponding to the register address to the third NAND flash input pin.