Clock generation circuit and semiconductor device including the same

• US 8,103,897 B2
• Filed: 08/27/2007
• Issued: 01/24/2012
• Est. Priority Date: 08/31/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Endo, Masami, Ikeda, Takayuki, Kawae, Daisuke, Kurokawa, Yoshiyuki
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US11/845,391
• Publication Number:
  US 20080054976A1
• Time in Patent Office: 1,611 Days
• Field of Search: None
• US Class Current: 713/500
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

Objects of the invention are to provide a clock generation circuit, in which, even when different clock signals are used among a plurality of circuits such as a transmitting circuit and a receiving circuit, stabilized communication is possible; and to provide a semiconductor device including the clock generation circuit. The clock generation circuit includes an edge detection circuit, a reference clock generation circuit, a reference clock counter circuit, and a frequency-divider circuit. The reference clock counter circuit is a circuit which outputs a counter value, which is obtained by counting the number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects an edge of a signal which is externally inputted to the edge detection circuit to when the edge detection circuit detects the next edge, to the frequency-divider circuit. The frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value.

Claims

1. A clock generation circuit comprising:

an edge detection circuit;

a reference clock generation circuit;

a reference clock counter circuit; and

a frequency-divider circuit,

wherein the edge detection circuit comprises a first latch circuit, a second latch circuit, an inverter circuit, and an AND circuit,

wherein the first latch circuit is electrically connected to the second latch circuit and the inverter circuit,

wherein the AND circuit is electrically connected to the second latch circuit and the inverter circuit,

wherein the AND circuit outputs a reset signal when the first latch circuit receives a first signal,

wherein the reference clock generation circuit outputs a reference clock signal,

wherein the reference clock counter circuit outputs a counter value obtained by counting a number of waves of the reference clock signal, and resets the counter value when the reference clock counter circuit receives the reset signal,

wherein the frequency-divider circuit generates a clock signal from the counter value, and

wherein a first cycle of the clock signal in a first period is longer than a second cycle of the clock signal in a second period.

2. The clock generation circuit according to claim 1, wherein the reference clock generation circuit is one of a ring oscillator and a quartz-crystal oscillator.

3. A clock generation circuit comprising:

an edge detection circuit;

a reference clock generation circuit;

a reference clock counter circuit; and

a frequency-divider circuit,

wherein the edge detection circuit comprises a first latch circuit, a second latch circuit, and a logic circuit,

wherein the first latch circuit electrically connected to the second latch circuit and the logic circuit,

wherein the logic circuit is electrically connected to the second latch circuit,

wherein the logic circuit outputs a reset signal when the first latch circuit receives a first signal,

wherein the reference clock generation circuit outputs a reference clock signal,

wherein the reference clock counter circuit outputs a counter value obtained by counting a number of waves of the reference clock signal, keeps the counter value when the counter value is equal to a predetermined value, and resets the counter value when the reference clock counter circuit receives the reset signal,

wherein the frequency-divider circuit generates a clock signal from the counter value,

wherein a first cycle of the clock signal in a first period is longer than a second cycle of the clock signal in a second period, and

wherein the reference clock counter circuit keeps the counter value in the first period.

4. The clock generation circuit according to claim 3, wherein the reference clock generation circuit is one of a ring oscillator and a quartz-crystal oscillator.

5. A clock generation circuit comprising:

an edge detection circuit;

a reference clock generation circuit;

a reference clock counter circuit; and

a frequency-divider circuit,

wherein the edge detection circuit includes a first latch circuit, a second latch circuit to which a signal outputted from the first latch circuit is inputted, an inverter circuit to which the signal outputted from the first latch circuit is inputted, and an AND circuit to which a signal outputted from the second latch circuit and a signal outputted from the inverter circuit are inputted,

wherein the AND circuit is a circuit which outputs a reset signal when the signal outputted from the second latch circuit and the signal outputted from the inverter circuit are different,

wherein the reference clock counter circuit is a circuit which outputs a counter value to the frequency-divider circuit, the counter value being obtained by counting a number of waves of a reference clock signal outputted from the reference clock generation circuit,

wherein the counter value is reset by the reset signal,

wherein the frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value and generates a clock signal from the counter value, and

wherein a first cycle of the clock signal in a first period is longer than a second cycle of the clock signal in a second period.

6. The clock generation circuit according to claim 5, wherein the reference clock generation circuit is one of a ring oscillator and a quartz-crystal oscillator.

7. A semiconductor device comprising:

an antenna;

an edge detection circuit;

a reference clock generation circuit;

a reference clock counter circuit; and

a frequency-divider circuit,

wherein the antenna outputs a first signal when the antenna receives a wireless signal transmitted from a reader/writer,

wherein the edge detection circuit comprises a first latch circuit, a second latch circuit, an inverter circuit, and an AND circuit,

wherein the first latch circuit is electrically connected to the second latch circuit and the inverter circuit,

wherein the AND circuit is electrically connected to the second latch circuit and the inverter circuit,

wherein the AND circuit outputs a reset signal when the first latch circuit receives the first signal,

wherein the reference clock generation circuit outputs a reference clock signal,

wherein the reference clock counter circuit outputs a counter value obtained by counting a number of waves of the reference clock signal, and resets the counter value when the reference clock counter circuit receives the reset signal,

wherein the frequency-divider circuit generates a clock signal from the counter value, and

wherein a first cycle of the clock signal in a first period is longer than a second cycle of the clock signal in a second period.

8. The semiconductor device according to claim 7, wherein the reference clock generation circuit is one of a ring oscillator and a quartz-crystal oscillator.

9. A semiconductor device comprising:

an antenna;

an edge detection circuit;

a reference clock generation circuit;

a reference clock counter circuit; and

a frequency-divider circuit,

wherein the antenna outputs a first signal when the antenna receives a wireless signal transmitted from a reader/writer,

wherein the edge detection circuit comprises a first latch circuit, a second latch circuit, and a logic circuit,

wherein the first latch circuit electrically connected to the second latch circuit and the logic circuit,

wherein the logic circuit is electrically connected to the second latch circuit,

wherein the logic circuit outputs a reset signal when the first latch circuit receives the first signal,

wherein the reference clock generation circuit outputs a reference clock signal,

wherein the reference clock counter circuit outputs a counter value obtained by counting a number of waves of the reference clock signal, keeps the counter value when the counter value is equal to a predetermined value, and resets the counter value when the reference clock counter circuit receives the reset signal,

wherein the frequency-divider circuit generates a clock signal from the counter value,

wherein a first cycle of the clock signal in a first period is longer than a second cycle of the clock signal in a second period, and

wherein the reference clock counter circuit keeps the counter value in the first period.

10. The semiconductor device according to claim 9, wherein the reference clock generation circuit is one of a ring oscillator and a quartz-crystal oscillator.

11. A semiconductor device for transmitting and receiving a signal wirelessly with a reader/writer, which is provided with an antenna, comprising:

an edge detection circuit;

a reference clock generation circuit;

a reference clock counter circuit; and

a frequency-divider circuit,

wherein the edge detection circuit includes a first latch circuit, a second latch circuit to which a signal outputted from the first latch circuit is inputted, an inverter circuit to which the signal outputted from the first latch circuit is inputted, and an AND circuit to which a signal outputted from the second latch circuit and a signal outputted from the inverter circuit are inputted,

wherein the AND circuit is a circuit which outputs a reset signal when the signal outputted from the second latch circuit and the signal outputted from the inverter circuit are different,

wherein the reference clock counter circuit is a circuit which outputs a counter value to the frequency-divider circuit, the counter value being obtained by counting a number of waves of a reference clock signal outputted from the reference clock generation circuit,

wherein the counter value is reset by the reset signal,

wherein the frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value and generates a clock signal from the counter value, and

wherein a first cycle of the clock signal in a first period is longer than a second cycle of the clock signal in a second period.

12. The semiconductor device according to claim 11, wherein the reference clock generation circuit is one of a ring oscillator and a quartz-crystal oscillator.