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Low overhead soft error tolerant flip flop

  • US 8,103,941 B2
  • Filed: 03/31/2008
  • Issued: 01/24/2012
  • Est. Priority Date: 03/31/2008
  • Status: Active Grant
First Claim
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1. A flip-flop circuit comprising:

  • a first stage configured to;

    receive an input data signal; and

    receive a first input clock signal; and

    a second stage comprising soft error recovery (SER) circuitry, wherein the second stage is configured to;

    receive a second input clock signal which is internally gated based on a state of the flip-flop;

    store a prebuffered data output on a first node; and

    store a feedback storage value on a second node different from the first node;

    wherein the SER circuitry is configured to;

    recover the prebuffered data value to an original value without a transition of a clock signal, in response to detecting an error; and

    recover the feedback value to an original value without a transition of a clock signal, in response to detecting an error.

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