Low overhead soft error tolerant flip flop

• US 8,103,941 B2
• Filed: 03/31/2008
• Issued: 01/24/2012
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Naffziger, Samuel D.
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US12/059,543
• Publication Number:
  US 20090249149A1
• Time in Patent Office: 1,394 Days
• Field of Search: 714/775, 714/798, 714/799, 714/780, 714/724, 714/733, 714/734, 714/30, 365/154, 365/189.06, 365/189.07, 365/226, 365/233.15, 327/200, 327/208, 327/212, 327/210, 327/211, 327/218
• US Class Current: 714/775
• CPC Class Codes: H03K 19/007 Fail-safe circuits
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

A system and method for soft error recovery (SER) within a flip-flop. A first stage of the flip-flop receives an ungated input clock signal. A second stage of the flip-flop receives a gated input clock signal. The second stage may also store a prebuffered data output and one or more feedback storage values on separate nodes. The flip-flop has SER circuitry used to recover the prebuffered data output and any feedback storage value without requiring a transition of a clock signal.

Claims

1. A flip-flop circuit comprising:

a first stage configured to;

receive an input data signal; and

receive a first input clock signal; and

a second stage comprising soft error recovery (SER) circuitry, wherein the second stage is configured to;

receive a second input clock signal which is internally gated based on a state of the flip-flop;

store a prebuffered data output on a first node; and

store a feedback storage value on a second node different from the first node;

wherein the SER circuitry is configured to;

recover the prebuffered data value to an original value without a transition of a clock signal, in response to detecting an error; and

recover the feedback value to an original value without a transition of a clock signal, in response to detecting an error.

2. The flip-flop circuit as recited in claim 1, wherein the SER circuitry comprises a first keeper circuit, a second keeper circuit, and a third keeper circuit.

3. The flip-flop circuit as recited in claim 2, wherein the first keeper circuit comprises:

a first output corresponding to the prebuffered data output;

a second input corresponds to a second output of the second keeper circuit; and

a third input corresponds to a third output of the second keeper circuit.

4. The flip-flop circuit as recited in claim 3, wherein the second keeper circuit comprises:

the second output;

the third output;

a fourth input is a fourth output of the third keeper circuit; and

a fifth input is the prebuffered data output.

5. The flip-flop circuit as recited in claim 4, wherein the third keeper circuit comprises:

the fourth output;

a sixth input that corresponds to a gated input clock signal;

a seventh input is the second output of the second keeper circuit; and

an eighth input is the third output of the second keeper circuit.

6. The flip-flop circuit as recited in claim 5, wherein the prebuffered data output and the fourth output of the third keeper circuit have a same logic value.

7. The flip-flop circuit as recited in claim 6, further comprising each of the second output and the third output of the second keeper circuit have an inverted logic value of the fourth output of the third keeper circuit.

8. The flip-flop circuit as recited in claim 1, wherein said first stage is a master latch and said second stage is a slave latch.

9. The flip-flop circuit as recited in claim 8, further comprising a transition of the second input clock signal is dependent upon a clock gating condition.

10. The flip-flop circuit as recited in claim 9, wherein a transition of the second input clock signal is prevented when both the input data signal and the prebuffered data output having a same logic value.

11. The flip-flop circuit as recited in claim 10, wherein the first logic value is a logic high value.

12. The flip-flop circuit as recited in claim 10, wherein the first logic value is a logic low value.

13. An error recovery method in a multi-stage flip-flop, the method comprising:

receiving in a first stage an input data signal and a first input clock signal;

receiving in a second stage a second input clock signal which is internally gated based on a state of the flip-flop;

storing in the second stage a prebuffered data output on a first node and a feedback storage value on a second node different from the first node;

recovering the prebuffered data value to an original value without a transition of a clock signal, in response to detecting an error; and

recovering the feedback value to an original value without a transition of a clock signal, in response to detecting an error.

14. The method as recited in claim 13, wherein the second stage comprises a first keeper circuit, a second keeper circuit, and a third keeper circuit.

15. The method as recited in claim 14, further comprising the first keeper circuit:

conveying the prebuffered data output as a first output;

receiving the second input clock signal as a first input;

receiving a second output of the second keeper circuit as a second input; and

receiving a third output of the second keeper circuit as a third input.

16. The method as recited in claim 15, further comprising the second keeper circuit:

conveying the second output;

conveying the third output;

receiving a fourth output of the third keeper circuit as a fourth input; and

receiving the prebuffered data output as a fifth input.

17. The method as recited in claim 16, further comprising the third keeper circuit:

conveying the fourth output;

receiving the second input clock signal as a sixth input;

receiving the second output of the second keeper circuit a seventh input; and

receiving the third output of the second keeper circuit as an eighth input.

18. The method circuit as recited in claim 17, wherein the prebuffered data output and the fourth output of the third keeper circuit have a same logic value.

19. The method as recited in claim 13, wherein said first stage is a master latch and said second stage is a slave latch.

20. The method as recited in claim 19, further comprising preventing a transition of the second input clock signal when both the input data signal and the prebuffered data output having a same logic value.