Method of manufacturing semiconductor device with wiring on side surface thereof

• US 8,105,856 B2
• Filed: 06/28/2004
• Issued: 01/31/2012
• Est. Priority Date: 04/23/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Noma, Takashi, Shinogi, Hiroyuki, Takai, Nobuyuki, Kitagawa, Katsuhiko, Tokushige, Ryoji, Otagaki, Takayasu, Ando, Tatsuya, Okigawa, Mitsuru
• Primary Examiner(s): MITCHELL, JAMES M
• Application Number:
  US10/876,532
• Publication Number:
  US 20040235270A1
• Time in Patent Office: 2,773 Days
• Field of Search: 438/33, 438/68, 438/113, 438460-464
• US Class Current: 438/33
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01021 Scandium [Sc]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10156 : at the periphery
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer comprising a first die and a second die, a top surface of the wafer being covered by a first insulation film, a first top wiring portion and a second top wiring portion being formed on the first insulation film so that the first and second top wiring portions are disposed above the first and second dice, respectively, the first top wiring portion being physically separated from the second top wiring portion and the first insulation film existing between the first top wiring portion and the second top wiring portion;

bonding a holding member to the wafer so that the holding member faces the top surface of the wafer;

etching a back surface of the wafer held by the holding member along a border between the first and second dice to expose a side surface and a back surface of the first die and a side surface and a back surface of the second die;

forming a second insulation film on the exposed side surfaces and back surfaces of the first and second dice;

forming a first bottom wiring portion on the second insulation film so that the first bottom wiring portion is physically in contact with the first top wiring portion and extends to the back surface of the first die;

forming a second bottom wiring portion on the second insulation film so that the second bottom wiring portion is physically in contact with the second top wiring portion and extends to the back surface of the second die;

forming a first conductive terminal on the first bottom wiring portion and forming a second conductive terminal on the second bottom wiring portion; and

separating the first and second dice by cutting the holding member to produce the first semiconductor device comprising the first top and bottom wiring portions and a cut holding member and a second semiconductor device comprising the second top and bottom wiring portions and another cut holding member,

wherein the forming of the first and second bottom wiring portions comprises exposing a back surface of each of the first and second top wiring portions and connecting the first and second bottom wiring portions to corresponding exposed back surfaces of the first and second top wiring portions, the exposed back surfaces of the first and second top wiring portions being on a plane of the top surface of the wafer.

2. The method of manufacturing a semiconductor device of claim 1, further comprising forming a protection film on the first and second bottom wiring portions so that the first and second conductive terminals are exposed through corresponding openings formed in the protection film.

3. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer comprising a first die and a second die, a top surface of the wafer being covered by a first insulation film, a first top wiring portion and a second top wiring portion being formed on the first insulation film so that the first and second top wiring portions are disposed above the first and second dice, respectively, the first top wiring portion being physically separated from the second top wiring portion and the first insulation film existing between the first top wiring portion and the second top wiring portion;

bonding a holding member to the wafer so that the holding member faces the top surface of the wafer;

etching a back surface of the wafer held by the holding member at a border between the first and second dice to expose a side surface and a back surface of the first die and a side surface and a back surface of the second die;

forming a second insulation film on the exposed side surfaces and back surfaces of the first and second dice;

forming a first bottom wiring portion on the second insulation film so that the first bottom wiring portion is physically in contact with the first top wiring portion and extends to the back surface of the first die;

forming a second bottom wiring portion on the second insulation film so that the second bottom wiring portion is physically in contact with the second top wiring portion and extends to the back surface of the second die;

forming a first conductive terminal on the first bottom wiring portion and forming a second conductive terminal on the second bottom wiring portion; and

separating the first and second dice by cutting the holding member to produce the first semiconductor device comprising the first top and bottom wiring portions and a cut holding member and a second semiconductor device comprising the second top and bottom wiring portions and another cut holding member,

wherein the forming of the first and second bottom wiring portions comprises exposing a back surface of each of the first and second top wiring portions and connecting the first and second bottom wiring portions to corresponding exposed back surfaces of the first and second top wiring portions, the exposed back surfaces of the first and second top wiring portions being on a plane of the top surface of the wafer.