Approach for bonding dies onto interposers

• US 8,105,875 B1
• Filed: 10/14/2010
• Issued: 01/31/2012
• Est. Priority Date: 10/14/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Jeng, Shin-Puu, Hou, Shang-Yun, Lin, Jing-Cheng, Chiou, Wen-Chih, Tu, Hung-Jung, Hu, Hsien-Pin
• Primary Examiner(s): Le, Thao P.
• Application Number:
  US12/904,835
• Time in Patent Office: 474 Days
• Field of Search: 438/107
• US Class Current: 438/107
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05005 Structure
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

Claims

1. A method comprising:

providing an interposer wafer comprising;

a substrate; and

a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate;

bonding a plurality of dies onto a front surface of the interposer wafer;

after the step of bonding the plurality of dies, filling a molding compound into gaps between the plurality of dies;

grinding the molding compound and a top surface of the plurality of dies;

after the step of grinding on the molding compound, performing a grinding on a backside of the substrate to expose the plurality of TSVs; and

forming a plurality of metal bumps on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

2. The method of claim 1, further comprising bonding a carrier over the plurality of dies before grinding the backside of the substrate.

3. The method of claim 1 further comprising:

after the step of performing the grinding on the molding compound, applying an adhesive to top surfaces of the plurality of dies; and

mounting a carrier over the top surfaces of the plurality of dies through the adhesive.

4. The method of claim 1 further comprising mounting a carrier over the plurality of dies and the molding compound through a first adhesive before performing the grinding on the backside of the substrate.

5. The method of claim 1 further comprising:

after the step of bonding the plurality of dies, filling an adhesive into gaps between the plurality of dies; and

mounting a carrier over top surfaces of the dies through the adhesive.

6. The method of claim 1, wherein the interposer wafer comprises no active devices therein.

7. The method of claim 6, wherein the interposer wafer comprises no transistor therein.

8. A method comprising:

providing an interposer wafer comprising;

a substrate; and

a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate;

bonding a plurality of dies onto a front side of the interposer wafer;

filling a molding compound into gaps between the plurality of dies;

performing a grinding on the molding compound;

after the step of performing the grinding on the molding compound, performing a grinding on a backside of the substrate to expose the plurality of TSVs; and

forming a plurality of metal bumps on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

9. The method of claim 8, wherein during the step of performing the grinding on the molding compound, top surfaces of the plurality of dies are also grinded to reduce thicknesses of the plurality of dies.

10. The method of claim 8 further comprising mounting a carrier over the plurality of dies and the molding compound through a first adhesive, before performing the grinding on the backside of the substrate.

11. The method of claim 10 further comprising, after the step of mounting the carrier and before the step of performing the grinding on the backside of the substrate, adding a second adhesive on edges of the interposer wafer.

12. The method of claim 8, wherein the interposer wafer comprises no active devices therein.

13. The method of claim 12, wherein the interposer wafer comprises no transistors therein.