Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout

• US 8,105,895 B2
• Filed: 02/17/2011
• Issued: 01/31/2012
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Wang, Xiaobin, Ho, Moses
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US12/932,163
• Publication Number:
  US 20110140194A1
• Time in Patent Office: 348 Days
• Field of Search: 257/330, 257/334, 257/475, 257/476, 257/484, 257/E27.04, 257/E29.013, 257/E21.616, 438/237
• US Class Current: 438/237
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

Claims

1. A method for manufacturing a semiconductor power device to form an active cell area with a plurality of power transistor cells comprising:

forming said power transistor cells in said active cell area with separated body regions having gaps between two adjacent power transistors and forming a planar Schottky diode in each of said power transistor cells by depositing a Schottky junction barrier metal covering areas above said gaps between separated body regions for applying a heavy body doped region disposed in said separated body regions surrounding said Schottky diode to adjust a leakage current of said Schottky diode in each of said power transistor cells; and

wherein;

said step of forming said planar Schottky diodes further comprising a step of carrying out a shallow Shannon implant to form a Sharon implant region in said gaps between said separated body regions of two adjacent power transistor cells for adjusting a leakage current of said Schottky diode.

2. A method for manufacturing a semiconductor power device to form an active cell area with a plurality of power transistor cells comprising:

forming said power transistor cells in said active cell area with separated body regions having gaps between two adjacent power transistors and forming a planar Schottky diode in each of said power transistor cells by depositing a Schottky junction barrier metal covering areas above said gaps between separated body regions for applying a heavy body doped region disposed in said separated body regions surrounding said Schottky diode to adjust a leakage current of said Schottky diode in each of said power transistor cells; and

wherein;

said step of forming said planar Schottky diodes further comprising a step of carrying out a counter doped implant for forming a lower and smooth variation of dopant along a vertical direction on a top portion of an epitaxial layer in regions for forming Schottky junction barrier.