Method for making a trench MOSFET with shallow trench structures

• US 8,105,903 B2
• Filed: 09/21/2009
• Issued: 01/31/2012
• Est. Priority Date: 09/21/2009
• Status: Expired due to Fees

• Current Assignee: Memoir Systems, Inc (Cisco Systems, Inc.), Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hsieh, Fu-Yuan
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): WITHERS, GRANT S
• Application Number:
  US12/585,645
• Publication Number:
  US 20110070708A1
• Time in Patent Office: 862 Days
• Field of Search: 438/270
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for making a trench MOSFET with shallow trench structures with a thick trench bottom is disclosed. The improved method resolves the problem of deterioration of breakdown voltage resulted by LOCOS having a bird'"'"'s beak shape introduced in prior art, and at the same time, the inventive device has a lower Qgd and lower Rds.

Claims

1. A method for making a trench MOSFET with a thick trench bottom oxide, comprising:

forming a plurality of gate trenches in an epitaxial layer of a first conductivity doping type;

forming a first insulation layer along an inner surface of said gate trenches and a top surface of said epitaxial layer;

depositing a layer of un-doped poly silicon or amorphous silicon onto said first insulation layer;

depositing a nitride layer onto said un-doped poly silicon or amorphous silicon and carrying out a nitride anisotropic etching to leave said nitride layer only on sidewalls of said gate trenches;

oxidizing said un-doped poly silicon or amorphous silicon on bottoms of said gate trenches to form said thick trench bottom oxide having thickness greater than said first insulation layer along the sidewalls of said gate trenches; and

removing said nitride layer from the sidewalls of said gate trenches.

2. The method of claim 1, wherein said un-doped poly silicon is deposited at 650°

C. or above.

3. The method of claim 1, wherein said un-doped amorphous silicon is deposited below 650°

C.

4. The method of claim 1, wherein before forming said first insulation layer, further comprises:

depositing a layer of hard mask covering said epitaxial layer over a substrate layer;

applying a trench mask onto said hard mask, and etching said hard mask and said epitaxial layer to form said gate trenches;

growing a sacrificial oxide along the inner surface of said gate trenches and then removing said sacrificial oxide;

forming a screen oxide along the inner surface of said gate trenches and carrying out an ion implantation to form doped regions of said first conductivity doping type around the bottoms of said gate trenches with doping concentration heavier than said epitaxial layer; and

removing said screen oxide and said hard mask.

5. The method of claim 1, wherein before forming said first insulation layer, further comprises:

depositing a layer of hard mask covering said epitaxial layer over a substrate layer;

applying a trench mask onto said hard mask, and etching said hard mask and said epitaxial layer to form said gate trenches;

removing said hard mask;

growing a sacrificial oxide along the inner surface of said gate trenches and then removing said sacrificial oxide;

forming a screen oxide along the inner surface of said gate trenches and carrying out an ion implantation to form doped regions around the bottoms of said gate trenches and near the top surface of said epitaxial layer; and

removing said screen oxide.

6. The method of claim 1, wherein after removing said nitride layer, further comprises:

depositing a doped poly silicon layer or a combination of a doped poly silicon layer and a non-doped poly silicon layer to fill said gate trenches and then etching back to form a plurality of trenched gates.

7. The method of claim 6, wherein after forming said trenched gates, further comprises:

applying a body mask;

carrying out a body dopant ion implantation and driving-in said body dopant to form a body region of a second conductivity doping type;

applying a source mask; and

carrying out a source dopant ion implantation.

8. The method of claim 7, wherein after carrying out said source dopant ion implantation, further comprises:

depositing a second insulation layer covering the top surface of said epitaxial layer and said trenched gates;

applying a source-body contact mask, and etching through said second insulation layer and said source region, and extending into said body region to form source-body contact trenches;

applying a gate contact mask and etching through said second insulation layer and extending into at least one of said trenched gates to form gate contact trench;

carrying out a body contact dopant ion implantation to form a heavily doped body contact region of said second conductivity doping type underneath each of said source-body contact trenches and activating said body contact dopant by a RTA;

depositing a barrier layer of Ti/TiN or Co/TiN or Ta/TiN and W metal successively and then etching back to form a metal plug in each of said source-body contact trenches and said gate contact trench; and

depositing a resistance-reduction layer Ti or Ti/TiN and a metal layer of Al alloys or Cu, and patterning by applying a metal mask to form a source metal and a gate metal, respectively.

9. The method of claim 7, wherein after forming said trenched gates and before applying said body mask, further comprises applying a guard ring mask and carrying out an ion implantation to form a guard ring of said second conductivity doping type in a termination area.

10. The method of claim 7 further comprises driving-in said source dopant after carrying out said source dopant ion implantation.

11. The method of claim 8, wherein said gate metal also serves as a field metal plate beyond said body region and overlaps said epitaxial layer ranging from 2 to 10 μ

m.

12. A method for making a trench MOSFET, comprising:

depositing a hard mask covering an epitaxial layer of a first conductivity doping type over a substrate layer;

applying a trench mask onto said hard mask, and etching said hard mask and said epitaxial layer to form a plurality of gate trenches;

growing a sacrificial oxide along an inner surface of said gate trenches and then removing said sacrificial oxide;

forming a screen oxide along the inner surface of said gate trenches and carrying out an ion implantation to form doped regions of said first conductivity doping type around bottoms of said gate trenches with doping concentration heavier than said epitaxial layer;

removing said screen oxide and said hard mask;

forming a first insulation layer as a gate oxide along the inner surface of said gate trenches and a top surface of said epitaxial layer;

depositing a layer of un-doped poly silicon or amorphous silicon onto said first insulation layer;

depositing a nitride layer onto said un-doped poly silicon or amorphous silicon and carrying out a nitride anisotropic etching to leave said nitride layer only on sidewalls of said gate trenches;

oxidizing said un-doped poly silicon or amorphous silicon on the bottoms of said gate trenches and the top surface of said epitaxial layer; and

removing said nitride layer from the sidewalls of said gate trenches.

13. A method for making a trench MOSFET, comprising:

depositing a hard mask covering an epitaxial layer of a first conductivity doping type over a substrate;

applying a trench mask onto said hard mask, and etching said hard mask and said epitaxial layer to form a plurality of gate trenches;

removing said hard mask;

growing a sacrificial oxide along an inner surface of said gate trenches and then removing said sacrificial oxide;

forming a screen oxide along the inner surface of said gate trenches and carrying out an ion implantation to form doped regions of said first conductivity doping type around bottoms of said gate trenches with doping concentration heavier than said epitaxial layer;

removing said screen oxide;

forming a first insulation layer along the inner surface of said gate trenches and the top surface of said epitaxial layer;

depositing a layer of un-doped poly silicon or amorphous silicon onto said first insulation layer;

deposing a nitride layer onto said un-doped poly silicon or amorphous silicon and carrying out a nitride anisotropic etching to leave said nitride layer only on sidewalls of said gate trenches;

oxidizing said un-doped poly silicon or amorphous silicon on the bottoms of said gate trenches and the top surface of said epitaxial layer;

removing said nitride layer from the sidewalls of said gate trenches;

depositing a doped poly silicon layer or a combination of a doped poly silicon layer and a non-doped poly silicon layer to fill said gate trenches and then etching back to form a plurality of trenched gates;

applying a body mask, and carrying out a body dopant ion implantation and driving-in said body dopant to form a body region of a second conductivity doping type;

applying a source mask and carrying out a source dopant ion implantation to form a source region of said first conductivity doping type;

depositing a second insulation layer covering the top surface of said epitaxial layer and said trenched gates;

applying a source-body contact mask, and etching through said second insulation layer and said source region, and extending into said body region to form source-body contact trenches; and

applying a gate contact mask, and etching through said second insulation layer and extending into at least one of said trenched gates to form gate contact trench.