Through-wafer interconnection

• US 8,105,941 B2
• Filed: 05/18/2006
• Issued: 01/31/2012
• Est. Priority Date: 05/18/2005
• Status: Active Grant

• Current Assignee: Kolo Medical, Ltd.
• Original Assignee: Kolo Technologies, Inc.
• Inventors: Huang, Yongli
• Primary Examiner(s): STARK, JARRETT J
• Application Number:
  US11/914,584
• Publication Number:
  US 20080203556A1
• Time in Patent Office: 2,084 Days
• Field of Search: 438/638, 438/639, 257/E21.577, 257/E21.585
• US Class Current: 438/638
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A through-wafer interconnect and a method for fabricating the same are disclosed. The method starts with a conductive wafer to form a patterned trench by removing material of the conductive wafer. The patterned trench extends in depth from the front side to the backside of the wafer, and has an annular opening generally dividing the conductive wafer into an inner portion and an outer portion whereby the inner portion of the conductive wafer is insulated from the outer portion and serves as a through-wafer conductor. A dielectric material is formed or added into the patterned trench mechanical to support and electrically insulate the through-wafer conductor. Multiple conductors can be formed in an array.

Claims

1. A method for fabricating through-wafer interconnects in a microelectronic structure, the method comprising:

providing a conductive wafer having a front side and a backside; and

forming a patterned trench in the conductive wafer by removing material of the conductive wafer, wherein the patterned trench has an annular circumferential opening dividing the conductive wafer along the opening into an inner portion and an outer portion whereby the inner portion of the conductive wafer is insulated from the outer portion and serves as a through-wafer conductor, and wherein the patterned trench comprises a first trench portion having a first cross-sectional size and a second trench portion having a second cross-sectional size different from the first cross-sectional size.

2. The method of claim 1 further comprising adding a filler material into the patterned trench to form a mechanical support between the inner portion and the outer portion to maintain the inner portion within the annular circumferential opening.

3. The method of claim 1 further comprising adding a dielectric material into the patterned trench to electrically insulate the inner portion from the outer portion.

4. The method of claim 1 further comprising:

forming the through-wafer conductor to have a first portion surrounded and defined by the first portion of the patterned trench and a second portion surrounded and defined by the second portion of the patterned trench; and

forming the second portion of the through-wafer conductor to have a smaller cross-sectional size than the first portion of the through-wafer conductor.

5. The method of claim 1 further comprising forming the conductive wafer has as a composite wafer having a top layer and a bottom layer that are bonded together.

6. The method of claim 5 wherein the top layer and the bottom layer of the conductive wafer are directly bonded together without an intervening layer of material.

7. The method of claim 1 wherein the top layer and the bottom layer of the conductive wafer are directly bonded together with an intervening material that serves as a stop material between the first trench portion and the second trench portion.

8. The method of claim 1 wherein the conductive wafer is a doped silicon wafer having a top section and a bottom section which have different doping levels.

9. The method of claim 1 wherein the forming the patterned trench comprises:

forming a first portion of the patterned trench from one of the front side and the backside; and

forming a second portion of the patterned trench from the other side.

10. The method of claim 9 wherein the forming the patterned trench further comprises oxidizing the first portion of the patterned trench to form a stop layer on a bottom of the first portion to define a stop position, and wherein the forming the second portion of the patterned trench stops when the second portion of the patterned trench reaches the stop position.

11. The method of claim 9 wherein the forming the patterned trench further comprises adding a dielectric material in at least one of the first and the second portions of the patterned trench.

12. The method of claim 1, wherein at least a portion of the patterned trench is further fine-patterned within trench opening with open passages interlined with lines of unremoved conductive wafer material.

13. The method of claim 12 further comprising adding a filler material between the lines of unremoved conductive wafer material.

14. The method of claim 12 further comprising oxidizing the lines of unremoved conductive wafer material.

15. The method of claim 14 further comprising adding a filler material between the oxidized lines of unremoved conductive wafer material.

16. The method of claim 1 wherein the forming the patterned trench comprises forming a plurality of patterned trenches similarly characterized.

17. The method of claim 16 wherein the plurality of patterned trenches are arranged side-by-side in an array with neighboring patterned trenches sharing a common trench side.

18. The method of claim 16 wherein the plurality of patterned trenches are arranged side-by-side in an array with neighboring patterned trenches separated by an intervening spacing.

19. The method of claim 18 wherein the intervening spacing is occupied by a conductive material for decoupling neighboring conductors.

20. The method of claim 19 wherein the conductive material in the intervening spacing comprises unremoved conductive material of the conductive wafer.

21. The method of claim 1 wherein the conductive wafer is a conductive silicon wafer, and the forming the patterned trench comprises:

forming the first portion of the patterned trench by etching from one of the front side and the backside of the conductive silicon wafer;

forming an oxide layer over surfaces of the first portion of the patterned trench;

removing at least part of the oxide layer on a bottom of the first portion of the patterned trench;

forming an enlarged cavity at the bottom of the first portion of the patterned trench by isotropic silicon etching;

forming a stop layer by oxidizing a bottom surface of the enlarged cavity; and

forming the second portion of the patterned trench by etching from the other one of the front side or the backside of the conductive silicon wafer to reach the stop layer.

22. A method for fabricating through-wafer interconnects in a microelectronic structure, the method comprising:

providing a conductive wafer having a front side and a backside;

forming a first portion of a patterned trench from one of the front side or the backside in the conductive wafer by removing material of the conductive wafer, the patterned trench having an annular circumferential opening dividing the conductive wafer along the opening into an inner portion and an outer portion so that the inner portion of the conductive wafer is located within the annular circumferential opening and insulated from the outer portion to form a through-wafer conductor, the first portion of the patterned trench being formed having a first pattern;

providing a stop material on a bottom of the first portion to define a stop position; and

forming a second portion of the patterned trench from the other of the front side and the backside, the forming the second portion of the patterned trench ceasing when the second portion of the patterned trench reaches the stop position, the second portion of the patterned trench being formed having a second pattern different from the first pattern of the first portion of the patterned trench.

23. The method of claim 22 further comprising adding a filler material into at least one of the first portion of the patterned trench or the second portion of the patterned trench to form a mechanical support between the inner portion and the outer portion to maintain the inner portion within the annular circumferential opening.

24. The method of claim 23 wherein the filler material is a dielectric material added into the patterned trench to electrically insulate the inner portion from the outer portion.

25. The method of claim 22 wherein first portion of the patterned trench has a first cross-sectional size and the second portion of the patterned trench has a second cross-sectional size different from the first cross-sectional size.

26. The method of claim 22 further comprising:

forming the through-wafer conductor to have a first portion surrounded and defined by the first portion of the patterned trench and a second portion surrounded and defined by the second portion of the patterned trench; and

forming the second portion of the through-wafer conductor to have a different cross-sectional size than the first portion of the through-wafer conductor.

27. The method of claim 22 further comprising forming the conductive wafer as a composite wafer having a top layer and a bottom layer that are bonded together.

28. The method of claim 27 wherein the top layer and the bottom layer of the conductive wafer are directly bonded together without an intervening layer of material.

29. The method of claim 27 wherein the top layer and the bottom layer of the conductive wafer are directly bonded together with an intervening material that also serves as the stop material.

31. The method of claim 22 wherein the conductive wafer is a doped silicon wafer having a top section and a bottom section, which have different doping levels.

32. The method of claim 22 wherein the providing the stop material comprises oxidizing the first portion of the patterned trench to form a stop layer on a bottom of the first portion of the patterned trench to define the stop position.

33. The method of claim 22 further comprising adding a dielectric material in at least one of the first portion of the patterned trench or the second portion of the patterned trench.

34. The method of claim 22, wherein at least a portion of the patterned trench is further fine-patterned within a trench opening with open passages interlined with lines of unremoved conductive wafer material.

35. The method of claim 34 further comprising adding a filler material between the lines of unremoved conductive wafer material.

36. The method of claim 34 further comprising oxidizing the lines of unremoved conductive wafer material.

37. The method of claim 22 wherein the forming the first portion of the patterned trench and the second portion of the patterned trench comprises forming a plurality of patterned trenches, each patterned trench having the first and second portions.

38. The method of claim 37 wherein the plurality of patterned trenches are arranged side-by-side in an array with neighboring patterned trenches sharing a common trench side.

39. The method of claim 37 wherein the plurality of patterned trenches are arranged side-by-side in an array with neighboring patterned trenches separated by an intervening spacing.

40. The method of claim 39 wherein the intervening spacing is occupied by a conductive material for decoupling neighboring conductors.

41. The method of claim 40 wherein the conductive material in the intervening spacing comprises unremoved conductive material of the conductive wafer.

42. The method of claim 22 wherein the conductive wafer is a conductive silicon wafer, and the providing the stop material comprises:

forming an enlarged cavity at a bottom of the first portion of the patterned trench by isotropic silicon etching; and

forming the stop material by oxidizing a bottom surface of the enlarged cavity to define a stop layer.

30. The method of 29 wherein the intervening material is an oxide layer formed on the one of the top layer or the bottom layer of the conductive wafer.

43. A method for fabricating through-wafer interconnects in a microelectronic structure, the method comprising:

providing a conductive wafer having a front side and a backside;

forming a first portion of a patterned trench from one of the front side or the backside in the conductive wafer by removing material of the conductive wafer, the patterned trench having an annular circumferential opening dividing the conductive wafer along the opening into an inner portion and an outer portion so that the inner portion of the conductive wafer is insulated from the outer portion to form a through-wafer conductor, the first trench portion having a first cross-sectional size;

providing a stop material on a bottom of the first portion to define a stop position; and

forming a second portion of the patterned trench from the other of the front side and the backside, the forming the second portion of the patterned trench stopping when the second portion of the patterned trench reaches the stop position, the second trench portion having a second cross-sectional size different from the first cross-sectional size of the first portion of the patterned trench.

44. The method of claim 43 further comprising adding a filler material into at least one of the first portion of the patterned trench or the second portion of the patterned trench to form a mechanical support between the inner portion and the outer portion to maintain the inner portion within the annular circumferential opening.

45. The method of claim 44 wherein the filler material is a dielectric material added into the patterned trench to electrically insulate the inner portion from the outer portion.

46. The method of claim 43 wherein the first cross-sectional size and the second cross-sectional size determine electrical and mechanical properties of a finished microelectronic structure.

47. The method of claim 43, further comprising:

forming the through-wafer conductor to have a first portion surrounded and defined by the first portion of the patterned trench and a second portion surrounded and defined by the second portion of the patterned trench; and

forming the second portion of the through-wafer conductor to have a different cross-sectional size than the first portion of the through-wafer conductor.

48. The method of claim 43 further comprising forming the conductive wafer as a composite wafer having a top layer and a bottom layer that are bonded together.

49. The method of claim 48 wherein the top layer and the bottom layer of the conductive wafer are directly bonded together without an intervening layer of material.

50. The method of claim 48 wherein the top layer and the bottom layer of the conductive wafer are directly bonded together with an intervening material that also serves as the stop material.

51. The method of claim 50 wherein the intervening material is the oxide layer formed on one of the top layer or the bottom layer of the conductive wafer.

52. The method of claim 43 wherein the conductive wafer is a doped silicon wafer having a top section and a bottom section which have different doping levels.

53. The method of claim 43 wherein the providing the stop material comprises oxidizing the first portion of the patterned trench to form a stop layer on a bottom of the first portion of the patterned trench to define the stop position.

54. The method of claim 43 further comprising adding a dielectric material in at least one of the first portion of the patterned trench or the second portion of the patterned trench.

55. The method of claim 43, wherein at least a portion of the patterned trench is further fine-patterned within a trench opening with open passages interlined with lines of unremoved conductive wafer material.

56. The method of claim 55 further comprising adding a filler material between the lines of unremoved conductive wafer material.

57. The method of claim 55 further comprising oxidizing the lines of unremoved conductive wafer material.

58. The method of claim 43 wherein the forming the first portion of the patterned trench and the second portion of the patterned trench comprises forming a plurality of patterned trenches, each patterned trench having the first and second portions.

59. The method of claim 58 wherein the plurality of patterned trenches are arranged side-by-side in an array with neighboring patterned trenches sharing a common trench side.

60. The method of claim 58 wherein the plurality of patterned trenches are arranged side-by-side in an array with neighboring patterned trenches separated by an intervening spacing.

61. The method of claim 60 wherein the intervening spacing is occupied by a conductive material for decoupling neighboring conductors.

62. The method of claim 61 wherein the conductive material in the intervening spacing comprises unremoved conductive material of the conductive wafer.

63. The method of claim 43 wherein the conductive wafer is a conductive silicon wafer, and the providing the stop material comprises:

forming an enlarged cavity at a bottom of the first portion of the patterned trench by isotropic silicon etching; and

forming the stop material by oxidizing a bottom surface of the enlarged cavity to define a stop layer.

64. A method for fabricating through-wafer interconnects in a microelectronic structure, the method comprising:

providing a conductive wafer having a front side and a backside;

forming a patterned trench in the conductive wafer by removing material of the conductive wafer from at least one of the front side or the backside, wherein the patterned trench has an annular circumferential opening dividing the conductive wafer along the opening into an inner portion and an outer portion, such that the inner portion of the conductive wafer is located within the annular circumferential opening and insulated from the outer portion to serve as a through-wafer conductor; and

adding a filler material into the patterned trench to maintain the through-wafer conductor within the annular circumferential opening during at least one subsequent fabricating step.