Field effect transistor

• US 8,106,382 B2
• Filed: 06/18/2007
• Issued: 01/31/2012
• Est. Priority Date: 06/21/2006
• Status: Active Grant

• Current Assignee: JDI Design and Development GK
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Saitoh, Tohru, Kawashima, Takahiro
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US12/305,824
• Publication Number:
  US 20100001259A1
• Time in Patent Office: 1,688 Days
• Field of Search: 257/24, 257/E29.168, 257/25, 257/29, 257/368, 257/E21.04, 257/E29.245, 257/E29.255, 438/3, 438/493, 977/62
• US Class Current: 257/24
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A source electrode 105 which is connected to a portion of at least one semiconductor nanostructure 103 among a plurality of semiconductor nanostructures, a drain electrode 106 connected to another portion of the semiconductor nanostructure 103, and a gate electrode 102 capable of controlling electrical conduction of the semiconductor nanostructure 103 are included. The semiconductor nanostructures 103 include a low concentration region 108 having a relatively low doping concentration and a pair of high concentration regions 107 having a higher doping concentration than that of the low concentration region 108 and being connected to both ends of the low concentration region 108. The doping concentration of the high concentration regions 107 is 1×10¹⁹ cm⁻³ or more; the length of the low concentration region 108 is shorter than a length of the gate electrode 102 along a direction from the source electrode 105 to the drain electrode 106; and the length of the gate electrode 102 is shorter than the interspace between the source electrode 105 and the drain electrode 106.

Claims

1. A field-effect transistor comprising:

a substrate;

a plurality of semiconductor nanostructures supported by the substrate;

a source electrode connected to a portion of at least one semiconductor nanostructure among the plurality of semiconductor nanostructures;

a drain electrode connected to another portion of the at least one semiconductor nanostructure;

an insulating film adjoining the at least one semiconductor nanostructure and functioning as a gate insulating film; and

a gate electrode being capable of controlling electrical conduction of the at least one semiconductor nanostructure via the insulating film, wherein,

each of the plurality of semiconductor nanostructures includes a low concentration region having a relatively low doping concentration and a pair of high concentration regions having a higher doping concentration than that of the low concentration region and being connected to both ends of the low concentration region;

the doping concentration of the high concentration region is 1×

10¹⁹ cm<sup>−

3</sup> or more; and

a length of the low concentration region is shorter than a length of the gate electrode along a direction from the source electrode to the drain electrode, and the length of the gate electrode is shorter than an interspace between the source electrode and the drain electrode,

wherein the length of the semiconductor nanostructures is longer than an interspace between the source electrode and the drain electrode.

2. The field-effect transistor of claim 1, wherein, one of the pair of high concentration regions of the at least one semiconductor nanostructure is connected to the source electrode;

the other of the pair of high concentration regions is connected to the drain electrode; and

at least a portion of the low concentration region has an overlap with the gate electrode.

3. The field-effect transistor of claim 1, wherein, one of the pair of high concentration regions of the at least one semiconductor nanostructure is connected to the source electrode;

the other of the pair of high concentration regions is connected to the drain electrode;

and the entire low concentration region has an overlap with the gate electrode.

4. The field-effect transistor of claim 1, wherein the following relational expression is satisfied:

(L_gate−

L_channel)>

(L_wire−

L_SD), where;

L_wire is a length of the semiconductor nanostructure;

L_channel is the length of the low concentration region;

L_gate is the length of the gate electrode; and

L_SD is the interspace between the source electrode and the drain electrode.

5. The field-effect transistor of claim 1, wherein the following relational expression is satisfied:

(L_gate+L_channel)>

(L_wire−

L_SD), where;

L_wire is a length of the semiconductor nanostructure;

L_channel is the length of the low concentration region;

L_gate is the length of the gate electrode; and

L_SD is the interspace between the source electrode and the drain electrode.

6. The field-effect transistor of claim 1, wherein the doping concentration of the high concentration region is in a range from 1×

10¹⁹ to 1×

10²² cm<sup>−

3</sup>; and

the doping concentration of the low concentration region is 10% or less of the doping concentration of the high concentration region.

7. The field-effect transistor of claim 6, wherein the doping concentration of the low concentration region is in a range from 1×

10¹⁵ to 1×

10¹⁹ cm<sup>−

3</sup>.

8. The field-effect transistor of claim 1, wherein the plurality of semiconductor nanostructures include at least one semiconductor nanostructure which has no overlap with one of the source electrode and the drain electrode.

9. The field-effect transistor of claim 8, wherein the low concentration region of the at least one semiconductor nanostructure which has no overlap with one of the source electrode and the drain electrode has no overlap with the gate electrode.

10. The field-effect transistor of claim 1, wherein the semiconductor nanostructure is a semiconductor nanowire.

11. The field-effect transistor of claim 1, wherein the semiconductor nanostructure is a semiconductor nanowire which is fabricated by vapor-liquid-solid growth (VLS growth).

12. The field-effect transistor of claim 1, wherein the semiconductor nanostructure is a silicon nanowire which is fabricated by vapor-liquid-solid growth (VLS growth).

13. The field-effect transistor of claim 1, wherein the substrate is made of an organic material.

14. The field-effect transistor of claim 1, wherein the source electrode and the drain electrode overlap with the plurality of semiconductor nanostructures.

15. The field-effect transistor of claim 1, wherein the semiconductor nanostructures are nanowires, and the semiconductor nanostructures are arranged in a different direction from the direction from the source electrode toward the drain electrode.

16. A field-effect transistor comprising:

a substrate;

a plurality of semiconductor nanostructures supported by the substrate;

a source electrode connected to a portion of at least one semiconductor nanostructure among the plurality of semiconductor nanostructures;

a drain electrode connected to another portion of the at least one semiconductor nanostructure;

an insulating film adjoining the at least one semiconductor nanostructure and functioning as a gate insulating film; and

a gate electrode being capable of controlling electrical conduction of the at least one semiconductor nanostructure via the insulating film, wherein,

each of the plurality of semiconductor nanostructures includes a low concentration region having a relatively low doping concentration and a pair of high concentration regions having a higher doping concentration than that of the low concentration region and being connected to both ends of the low concentration region;

the doping concentration of the high concentration region is 1×

10¹⁹ cm<sup>−

3</sup> or more; and

a length of the low concentration region is shorter than a length of the gate electrode along a direction from the source electrode to the drain electrode, and the length of the gate electrode is shorter than an interspace between the source electrode and the drain electrode,

wherein at least one of the plurality of semiconductor nanostructures are connected to the source electrode and the drain electrode,

in at least one of the plurality of semiconductor nanostructures, the low concentration region has an overlap with the gate electrode,

and at least one of the plurality of semiconductor nanostructures have no connection with the source electrode or the drain electrode.

17. The field-effect transistor of claim 16, wherein, one of the pair of high concentration regions of the at least one semiconductor nanostructure is connected to the source electrode;

the other of the pair of high concentration regions is connected to the drain electrode; and

at least a portion of the low concentration region has an overlap with the gate electrode.

18. The field-effect transistor of claim 16, wherein, one of the pair of high concentration regions of the at least one semiconductor nanostructure is connected to the source electrode;

the other of the pair of high concentration regions is connected to the drain electrode;

and the entire low concentration region has an overlap with the gate electrode.

19. The field-effect transistor of claim 16, wherein the following relational expression is satisfied:

(L_gate−

L_channel)>

(L_wire−

L_SD), where;

L_wire is a length of the semiconductor nanostructure;

L_channel is the length of the low concentration region;

L_gate is the length of the gate electrode; and

L_SD is the interspace between the source electrode and the drain electrode.

20. The field-effect transistor of claim 16, wherein the following relational expression is satisfied:

(L_gate+L_channel)>

(L_wire−

L_SD), where;

L_wire is a length of the semiconductor nanostructure;

L_channel is the length of the low concentration region;

L_gate is the length of the gate electrode; and

L_SD is the interspace between the source electrode and the drain electrode.