Wafer level packaging

• US 8,106,488 B2
• Filed: 10/06/2010
• Issued: 01/31/2012
• Est. Priority Date: 06/14/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chua, Swee Kwang, Boon, Suan Jeung, Chia, Yong Poo, Loo, Neo Yong
• Primary Examiner(s): Blum, David S
• Application Number:
  US12/898,896
• Publication Number:
  US 20110018143A1
• Time in Patent Office: 482 Days
• Field of Search: 257/662, 257/734, 257/782, 257/E23.068
• US Class Current: 257/662
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures

Abstract

Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.

Claims

1. A die comprising:

an active area on a substrate;

an insulator on the active area;

first and second bond pads on the insulator and electrically connected to the active area;

a first contact;

a second contact;

a first trace connecting the first bond pad to the first contact, at least a portion of the first trace being placed on top of the insulator over a portion of the active area; and

a second trace connecting the second bond pad to the second contact, the second trace being nonparallel to the first trace.

2. The die of claim 1, wherein the second trace is substantially coplanar with the first trace.

3. The die of claim 1, wherein the first trace is substantially linearly aligned with the second contact and the first contact.

4. The die of claim 3, wherein the first trace is enlongate.

5. The die of claim 1, wherein the first trace is substantially linearly aligned with the first contact and the first bond pad.

6. The die of claim 5, wherein the first trace is enlongate.

7. The die of claim 1, wherein the first trace and the second trace are not connected.

8. The die of claim 1, wherein the active area includes an array of memory cells.

9. The die of claim 1, wherein the active area includes a logic device.

10. A die comprising:

an active area on a substrate having a first edge and a second edge opposite the first edge;

a first recess in the first edge;

a first contact in the first recess;

a second recess in the second edge;

a second contact in the second recess;

a first bond pad on the substrate and electrically connected to the active area;

a second bond pad on the substrate and electrically connected to the active area;

a first trace connecting the first bond pad to the first contact; and

a second trace connecting the second bond pad to the second contact, wherein the first recess extends from a first side of the substrate to a second side of the substrate opposing the first side, so that electrical connection to the active area can be made from either the first side or the second side.

11. The die of claim 10, wherein the first contact is open at the first edge so that electrical connection to the active area can be made from the first edge.

12. A die comprising:

a first side of a substrate;

a plurality of bond pads on the first side of the substrate;

a plurality of pairs of contacts on the substrate, wherein a first contact of the pairs is substantially linearly aligned on a plane of the first side of the substrate in a first direction with a second contact of the pair and a first bond pad of the plurality of bond pads;

a first trace connecting the first contact to the first bond pad; and

a second trace connecting a second bond pad of the plurality of bond pads to the second contact.

13. The die of claim 12, wherein the first trace is substantially linearly aligned with the first bond pad and the first edge contact.

14. The die of claim 13, wherein the second bond pad is offset from the first bond pad in a second direction that is different than the first direction.

15. The die of claim 14, wherein the plurality of pairs of contacts include edge contacts.

16. The die of claim 15, wherein the plurality of pairs of contacts include back contacts.

17. The die of claim 16, wherein the plurality of pairs of contacts include top contacts.

18. The die of claim 12, wherein the substrate includes an array of memory cells and a logic device.