Power-on-reset circuit with brown-out reset for multiple power supplies

• US 8,106,688 B2
• Filed: 11/18/2009
• Issued: 01/31/2012
• Est. Priority Date: 11/18/2009
• Status: Active Grant

• Current Assignee: Smartech Worldwide Limited
• Original Assignee: Smartech Worldwide Limited
• Inventors: Huang, Haitao, Zhang, Min, Yin, Liding
• Primary Examiner(s): NGUYEN, LONG T
• Application Number:
  US12/620,689
• Publication Number:
  US 20110115533A1
• Time in Patent Office: 804 Days
• Field of Search: 327/77, 327/78, 327/80, 327/81, 327/142, 327/143, 327/198
• US Class Current: 327/143
• CPC Class Codes: H03K 17/22 Modifications for ensuring a predetermined initial state when the supply voltage has been applied bi-stable generators H03K3/12
• CPC Class Codes: H03K 17/24 Storing the actual state when the supply voltage fails

Abstract

A power-on reset circuit includes a first circuit and a second circuit. The first circuit include a first NMOS transistor having a gate controlled by a low voltage supply VDD_L, a resistor connected between the source of the first NMOS transistor and a voltage supply VSS that is lower than VDD_L, and one or more diodes serially connected between a high voltage supply VDD_H and the drain of the first NMOS transistor. The second circuit includes a first PMOS transistor having a source connected to VDD_L, a second PMOS transistor having a source connected to the drain of first PMOS transistor, a second NMOS transistor connected between the drain of the second PMOS transistor and VSS, and an inverter configured to output a signal in response to the power on of the high voltage supply VDD_H and the low voltage supply VDD_L.

Claims

1. A power-on reset circuit, comprising:

a first circuit, comprising;

a first NMOS transistor having a gate controlled by a low voltage supply VDD_L;

a resistor connected between the source of the first NMOS transistor and a voltage supply VSS, wherein VSS is lower than VDD_L; and

one or more diodes serially connected between a high voltage supply VDD_H and the drain of the first NMOS transistor, wherein VDD_H≧

VDD_L; and

a second circuit, comprising;

a first PMOS transistor having a source connected to VDD_L;

a second PMOS transistor having a source connected to the drain of first PMOS transistor;

a second NMOS transistor connected between the drain of the second PMOS transistor and VSS, wherein the gates of the first PMOS transistor, the second PMOS transistor, and the second NMOS transistor are connected to the source of the first NMOS transistor; and

an inverter having an input connected to the drain of the second PMOS transistor and the drain of the second NMOS transistor, wherein the inverter is configured to output a signal RSTB in response to the power on and power off of the high voltage supply VDD_H and the low voltage supply VDD_L.

2. The power-on reset circuit of claim 1, wherein the one or more diodes in the first circuit comprise &

first diode connected between a high voltage supply VDD_H and the drain of the first NMOS transistor.

3. The power-on reset circuit of claim 2, wherein the one or more diodes in the first circuit comprise a second diode connected with the first diode and the drain of the first NMOS transistor.

4. The power-on reset circuit of claim 1, wherein the second circuit further comprises a third PMOS transistor having a gate connected to the input of the inverter, a source connected with the drain of first PMOS transistor, and a drain connected to VSS.

5. The power-on reset circuit of claim 1, wherein the inverter is powered by the low voltage supply VOD_L and the power supply VSS.

6. The power-on reset circuit of claim 1, wherein the inverter is configured to output a voltage substantially equal to VDD_L only when both the low voltage supply VDD_L and the high voltage supply VDD_H are at or above their respective predetermined voltages in power on.

7. The power-on reset circuit of claim 1, wherein the first diode and the second diode are diode-connected PMOS transistors.

8. The power-on reset circuit of claim 1, further comprising a third NMOS transistor between the one or more diodes and the first NMOS transistor, wherein the gate of the third NMOS transistor is controlled by a mid voltage supply VDD_M, wherein VDD_H≧

VDD_M≧

VDD_L.

9. The power-on reset circuit of claim 8, wherein the inverter is configured to output a signal RSTB in response to the power on and power off of the high voltage supply VDD_H, the mid voltage supply VDD_M, and the low voltage supply VDD_L.

10. The power-on reset circuit of claim 8, wherein the inverter is configured to output a voltage substantially equal to VDD_L only when the low voltage supply VDD_L, the mid voltage supply VDD_M, and the high voltage supply VDD_H are all at or above their respective predetermined voltages.

11. A power-on reset circuit, comprising:

a first circuit, comprising;

one or more cascode-connected NMOS transistors comprising a first NMOS transistor having a gate controlled by a low voltage supply VDD_L;

a resistor connected between a voltage supply VSS and the source of the first NMOS transistor and VSS, wherein VSS is lower than VDD_L; and

one or more diodes serially connected between a high voltage supply VDD_H and the drain of the first NMOS transistor, wherein VDD_H≧

VDD_L; and

a second circuit, comprising;

a first PMOS transistor having a source connected to VDD_L;

a second PMOS transistor having a source connected to the drain of first PMOS transistor;

a second NMOS transistor connected between the drain of the second PMOS transistor and VSS, wherein the gates of the first PMOS transistor, the second PMOS transistor, and the second NMOS transistor are connected to the source of the first NMOS transistor; and

an inverter having an input connected to the drain of the second PMOS transistor and the drain of the second NMOS transistor, wherein the inverter is powered by the low voltage supply VDD_L and the power supply VSS.

12. The power-on reset circuit of claim 11, wherein the one or more diodes in the first circuit comprise a first diode connected between a high voltage supply VDD_H and the drain of the first NMOS transistor.

13. The power-on reset circuit of claim 12, wherein the one or more diodes in the first circuit comprise a second diode connected with the first diode and the drain of the first NMOS transistor.

14. The power-on reset circuit of claim 11, wherein the first diode and the second diode are diode-connected PMOS transistors.

15. The power-on reset circuit of claim 11, wherein the one or more cascode-connected NMOS transistors in the first circuit comprises a third NMOS transistor between the first diode and the first NMOS transistor, wherein the gate of the third NMOS transistor is controlled by a mid voltage supply VDD_M, wherein VDD_H≧

VDD_M≧

VDD_L.

16. The power-on reset circuit of claim 15, wherein the inverter is configured to output a signal RSTB in response to the power on and power off of the high voltage supply VDD_H, the mid voltage supply VDD_M, and the low voltage supply VDD_L.

17. The power-on reset circuit of claim 15, wherein the inverter is configured to output a voltage substantially equal to VDD_L only when the low voltage supply VDD_L, the mid voltage supply VDD_M, and the high voltage supply VDD_H are all at or above their respective predetermined voltages.

18. The power-on reset circuit of claim 11, wherein the inverter is configured to output a voltage substantially equal to VDD_L only when both the low voltage supply VDD_L and the high voltage supply VDD_H are at or above their respective predetermined voltages in power on.

19. The power-on reset circuit of claim 11, wherein the second circuit further comprises a third PMOS transistor having a gate connected to the input of the inverter, a source connected with the drain of first PMOS transistor, and a drain connected to VSS.

20. The power-on reset circuit of claim 11, wherein VDD_H is approximately equal to 3.3 volt, wherein VDD_L is approximately equal to 1.8 volt.