Successive time-to-digital converter for a digital phase-locked loop

• US 8,106,808 B1
• Filed: 07/21/2010
• Issued: 01/31/2012
• Est. Priority Date: 07/21/2010
• Status: Active Grant

• Current Assignee: MACOM Connectivity Solutions, LLC (MACOM Technology Solutions Holdings, Inc.)
• Original Assignee: Applied Micro Circuits Corporation (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Pang, Simon, Cohen, Hanan
• Primary Examiner(s): Nguyen, Khai M
• Application Number:
  US12/841,131
• Time in Patent Office: 559 Days
• Field of Search: 341/155, 341/166
• US Class Current: 341/166
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00

Abstract

A successive time-to-digital converter (STDC) method is provided for supplying a digital word representing the ratio between a phase-locked loop PLL frequency synthesizer signal and a reference clock. The number of frequency synthesizer clock cycles per reference clock cycle is counted. A first difference is measured between a reference clock period and a corresponding frequency synthesizer clock period. In response to the first measurement, a second difference is measured between a delayed reference clock period and the corresponding frequency synthesizer clock period, where the second difference is less than the first difference. A third difference is measured as a time duration between the delayed reference clock period and the corresponding delayed frequency synthesizer clock period. The first and third difference measurements and the count of the number of frequency synthesizer clock cycles per reference clock cycle are used to calculate a digital error signal supplied to the frequency synthesizer.

Claims

1. A successive time-to-digital converter (STDC) comprising:

a frequency detector having an input to accept a reference clock, input to accept a frequency synthesizer clock from a frequency synthesizer, and an output to supply a count of the number of frequency synthesizer clock cycles per reference clock cycle;

a first TDC having an input to accept the reference clock, and input to accept the frequency synthesizer clock, the first TDC measuring a first difference between an edge of a reference clock period and a corresponding edge of a frequency synthesizer clock period, providing the first difference measurement at an output, and providing the frequency synthesizer clock delayed a full cycle;

a phase interpolator having an input to accept the reference clock, an input to accept the frequency synthesizer clock, and an input to accept the first difference measurement, the phase interpolator supplying the reference clock delayed to create a second difference between the edge of the delayed reference clock period and the corresponding edge of the frequency synthesizer clock period, where the second difference is less than the first difference;

a second TDC having an input to accept the delayed reference clock period, and input to accept the delayed frequency synthesizer clock, the second TDC measuring a third difference between the edge of the delayed reference clock period and the corresponding edge of the delayed frequency synthesizer clock period, and providing the third difference measurement as a time duration; and

,

a digital signal processor (DSP) having an input to accept the third difference measurement, an input to accept the first difference measurement, an input to accept the count from the frequency detector, and an output to supply a digital error signal to the frequency synthesizer.

2. The STDC of claim 1 wherein the DSP supplies a digital error signal to the frequency synthesizer selected from a group consisting of a frequency error signal, a phase error signal, and both a phase and frequency error signal.

3. The STDC of claim 1 wherein the first TDC supplies the first difference measurement as a digital word representing the relationship between the edge of the reference clock and a phase of the frequency synthesizer clock.

4. The STDC of claim 3 wherein the first TDC includes:

n serially connected delay circuits to accept the frequency synthesizer clock, supplying n frequency synthesizer clock phases; and

n latches, each latch having a signal input connected to receive a corresponding frequency synthesizer clock phase, a clock input connected to receive the reference clock, and an output to supply a corresponding bit in an n-bit first difference measurement signal.

5. The STDC of claim 1 wherein the phase interpolator includes:

n serially connected delay circuits to accept the reference clock, supplying n reference clock phases; and

,

a multiplexer (MUX) having signal inputs to accept the n reference clock phases and a control input to accept the first difference measurement.

6. The STDC of claim 1 wherein the frequency detector includes:

a counter having an input to accept the frequency synthesizer clock, an input to accept an enable signal from the DSP, and an output to supply a tally triggered by the enable signal; and

,

a latch having a signal input to accept the tally, and clock input connected to receive the reference clock, and an output to supply the count of the number of frequency synthesizer clock cycles per reference clock cycle.

7. The STDC of claim 1 wherein the second TDC supplies the third difference measurement as a digital word representing the relationship between the edge of the delayed reference clock and a phase of the delayed frequency synthesizer clock.

8. The STDC of claim 7 wherein the second TDC includes:

m serially connected delay circuits to accept the delayed frequency synthesizer clock, supplying m phases of the delayed frequency synthesizer clock; and

,

m latches, each latch having a signal input connected to receive a corresponding phase of the delayed synthesizer clock, a clock input connected to receive the delayed reference clock, and an output to supply a corresponding bit in an m-bit third difference measurement signal.

9. The STDC of claim 8 wherein the second TDC is selectively enabled in response to a signal from the DSP.

10. A successive time-to-digital converter (STDC) method for supplying a digital word representing the ratio between a phase-locked loop PLL frequency synthesizer signal and a reference clock, the method comprising:

accepting a reference clock;

accepting a frequency synthesizer signal;

counting a number of frequency synthesizer clock cycles per reference clock cycle;

measuring a first difference between an edge of a reference clock period and a corresponding edge of a frequency synthesizer clock period;

in response to the first measurement, measuring a second difference between an edge of a delayed reference clock period and the corresponding edge of the frequency synthesizer clock period, where the second difference is less than the first difference;

measuring a third difference as a time duration between the edge of the delayed reference clock period and the corresponding edge of a frequency synthesizer clock period delayed a full period;

using the third difference measurement, the first difference measurement, and the count of the number of frequency synthesizer clock cycles per reference clock cycle, calculating a digital error signal; and

,

supplying the digital error signal to a frequency synthesizer.

11. The method of claim 10 wherein supplying the digital error signal includes supplying a signal selected from a group consisting of a frequency error signal, a phase error signal, and both a phase and frequency error signal.

12. The method of claim 10 wherein measuring the first difference includes representing the measurement of the first difference as a digital word.

13. The method of claim 12 wherein measuring the first difference includes:

accepting the frequency synthesizer clock;

creating n frequency synthesizer clock phases;

latching each frequency synthesizer clock phase;

clocking the latched frequency synthesizer phases with the reference clock; and

,

supplying an n-bit digital word representing the measurement of the first difference.

14. The method of claim 10 wherein measuring the second difference includes:

accepting the reference clock;

creating n reference clock phases; and

,

multiplexing the n reference clock phases in response to the measurement of the first difference.

15. The method of claim 10 wherein counting the number of frequency synthesizer clock cycles per reference clock cycle includes:

accepting the frequency synthesizer clock;

in response to an enable signal, creating a tally of frequency synthesizer clock cycles;

latching the tally; and

,

clocking the latched tally with the reference clock, to supply the count.

16. The method of claim 10 wherein measuring the third difference includes representing the measurement of the third difference as a digital word.

17. The method of claim 16 wherein measuring the third difference includes:

accepting the delayed frequency synthesizer clock;

creating m phases of the delayed frequency synthesizer clock;

latching each phase of the delayed synthesizer clock;

clocking the latched phases of the delayed frequency synthesizer clock with the delayed reference clock; and

,

supplying an m-bit digital word representing the measurement of the third difference.

18. The method of claim 17 wherein measuring the first, second, and third differences includes selectively enabling the measurement of the first, second, and third differences.