Distributed write data drivers for burst access memories

• US 8,107,304 B2
• Filed: 12/18/2009
• Issued: 01/31/2012
• Est. Priority Date: 12/23/1994
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Merritt, Todd A., Manning, Troy A.
• Primary Examiner(s): NGUYEN, VIET Q
• Application Number:
  US12/642,414
• Publication Number:
  US 20100097868A1
• Time in Patent Office: 774 Days
• Field of Search: 365/189.16, 365/189.05, 365/189.08, 365/233.5, 365/233.1, 365/230.06, 365/203
• US Class Current: 365/189.16
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.

Claims

1. A method of storing data in a system, comprising:

requesting the system to enter read mode;

providing a first column address from a microprocessor to a burst access memory;

providing a first plurality of data bits to the memory;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first plurality of data bits in a portion of the memory dependent on the first column address;

automatically providing a second column address to the memory that is not provided by the microprocessor without the requirement of advancing an address counter within the memory to provide a second address;

providing a second plurality of data bits to the memory;

generating an equilibration signal synchronously with an access cycle strobe signal;

asserting the equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second plurality of data bit in another portion of the memory dependent on the second column address, in response to deasserting the equilibration signal.

2. The method of claim 1, wherein the write enable signal is an active-low signal.

3. A method, comprising:

requesting the system to enter read mode;

providing a memory device having a pinout consisting of a /RAS input pin, a /CAS input pin, a /WE input pin, eight or more address input pins, two or more data output pins, and a /OE input pin;

initiating a burst mode access of the memory device; and

responding to signal transitions occurring only at the /CAS input pin during the burst mode access.

4. The method of claim 3, wherein the recited steps are initiated in the recited order.

5. The method of claim 3, wherein the memory device is a burst extended data out dynamic random access memory device.

6. The method of claim 3, including gating an equilibration signal with a read command and a high state on the /WE input pin.

7. The method of claim 3, wherein performing a burst mode access of the memory device comprises:

providing a first column address to the memory from a microprocessor;

providing a first plurality of data bits to the memory;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first plurality of data bits in a portion of the memory dependent on the first column address;

automatically providing a second column address to the memory that is not provided by the microprocessor without the requirement of advancing an address counter within the memory to provide a second address;

providing a second plurality of data bits to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second plurality of data bit in another portion of the memory dependent on the second column address, in response to deasserting the equilibration signal.

8. The method of claim 7, including generating the equilibration signal synchronously with an access cycle strobe signal.

9. A method comprising:

requesting the system to enter read mode;

initiating a burst mode access of a memory device having a pinout consisting of a /RAS input pin, a /CAS input pin, a /WE input pin, eight or more address input pins, two or more data output pins, and a /OE input pin; and

during the burst mode access, generating memory addresses within the memory device in response to corresponding signal transitions at the /CAS input pin.

10. The method of claim 9, wherein the burst mode access comprises a burst read cycle.

11. The method of claim 9, wherein generating memory addresses within the memory devices occurs in response to falling edge signal transitions at the /CAS input pin.

12. The method of claim 9, including asserting an equilibrate signal within the memory using the read command.

13. The method of claim 9, wherein performing a burst mode access of the memory device comprises:

providing a first column address to the memory from a microprocessor;

providing a first plurality of data bits to the memory;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first plurality of data bits in a portion of the memory dependent on the first column address;

automatically providing a second column address to the memory that is not provided by the microprocessor without the requirement of advancing an address counter within the memory to provide a second address;

providing a second plurality of data bits to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second plurality of data bit in another portion of the memory dependent on the second column address, in response to deasserting the equilibration signal.

14. The method of claim 13, including generating the equilibration signal synchronously with an access cycle strobe signal.

15. The method of claim 13, wherein the recited steps are initiated in the recited order.