Shift register and display device including the same
First Claim
1. A shift register comprising a plurality of stages, wherein stages of the plurality of stages are connected to each other and a current stage thereof generates an output signal in response to any one of a plurality of clock signals,wherein each of the stages comprises:
- a driving unit which charges to a predetermined voltage in response to one of an output start signal and an output signal of a previous stage, and which generates the output signal in response to any one of the clock signals; and
a discharge unit which discharges the predetermined voltage in response to an output signal of a next stage,wherein the driving unit comprises;
an input unit which outputs a first voltage in response to one of the output start signal and an output signal of the previous stage; and
an output unit which charges to the first voltage and generates the output signal in response to any one of the clock signals,wherein each of the clock signals having a duty ratio of less than 50% and a different phase from each of the other clock signals,wherein the output signal of the output unit is transmitted to a gate line and the next stage,wherein each of high levels of the clock signals do not overlap each other, andwherein the clock signals for some stages disposed on left side of the panel or the other stages disposed on right side of the panel have high value with a frequency of every 4 horizontal periods.
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Accused Products
Abstract
A shift register comprises stages connected to each other, in which each stage generates an output signal in response to any one of clock signals and an output from each of two different stages. Each clock signal has a duty ratio of less than 50% and a different phase from each of the other clock signals. A display device includes pixels, signal lines, and first and second shift registers each having stages connected to each other and generating output signals to signal lines. Each stage includes a set terminal, a reset terminal, a clock terminal, and first and second output terminals.
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Citations
21 Claims
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1. A shift register comprising a plurality of stages, wherein stages of the plurality of stages are connected to each other and a current stage thereof generates an output signal in response to any one of a plurality of clock signals,
wherein each of the stages comprises: -
a driving unit which charges to a predetermined voltage in response to one of an output start signal and an output signal of a previous stage, and which generates the output signal in response to any one of the clock signals; and a discharge unit which discharges the predetermined voltage in response to an output signal of a next stage, wherein the driving unit comprises; an input unit which outputs a first voltage in response to one of the output start signal and an output signal of the previous stage; and an output unit which charges to the first voltage and generates the output signal in response to any one of the clock signals, wherein each of the clock signals having a duty ratio of less than 50% and a different phase from each of the other clock signals, wherein the output signal of the output unit is transmitted to a gate line and the next stage, wherein each of high levels of the clock signals do not overlap each other, and wherein the clock signals for some stages disposed on left side of the panel or the other stages disposed on right side of the panel have high value with a frequency of every 4 horizontal periods. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A shift register comprising a plurality of stages, wherein some stages of the plurality of stages are disposed on left side of a panel and the other stages of the plurality of stages are disposed on right side of the panel,
wherein each of the stages comprises: -
a driving unit which charges to a predetermined voltage in response to one of an output start signal and an output signal of a previous stage, and which generates the output signal in response to any one of the clock signals; and a discharge unit which discharges the predetermined voltage in response to an output signal of a next stage, wherein the driving unit comprises; an input unit which outputs a first voltage in response to one of the output start signal and an output signal of the previous stage; and an output unit which charges to the first voltage and generates the output signal in response to any one of the clock signals, wherein some stages disposed on left side of the panel are connected to each other and the other stages disposed on right side of the panel are connected to each other, wherein each of the clock signals having a duty ratio of less than 50% and a different phase from each of the other clock signals, wherein some stages disposed on left side of the panel and the other stages disposed on right side of the panel are alternatively connected to gate lines, and wherein the clock signals for some stages disposed on left side of the panel or the other stages disposed on right side of the panel have high value with a frequency of every 4 horizontal periods. - View Dependent Claims (9, 10, 11)
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12. A shift register comprising a plurality of stages, wherein some stages of the plurality of stages are disposed on left side of a panel and the other stages of the plurality of stages are disposed on right side of the panel,
wherein each of the stages comprises: -
a driving unit which charges to a predetermined voltage in response to one of an output start signal and an output signal of a previous stage, and which generates the output signal in response to any one of the clock signals; and a discharge unit which discharges the predetermined voltage in response to an output signal of a next stage, wherein the driving unit comprises; an input unit which outputs a first voltage in response to one of the output start signal and an output signal of the previous stage; and an output unit which charges to the first voltage and generates the output signal in response to any one of the clock signals, wherein some stages disposed on left side of the panel are connected to each other and the other stages disposed on right side of the panel are connected to each other, wherein the output signal of the output unit is transmitted to a gate line and the next stage; wherein some stages disposed on left side of the panel and the other stages disposed on right side of the panel are alternatively connected to gate lines, and wherein the clock signals for some stages disposed on left side of the panel or the other stages disposed on right side of the panel have high value with a frequency of every 4 horizontal periods. - View Dependent Claims (13, 14)
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15. A shift register comprising a plurality of stages, wherein some stages of the plurality of stages are disposed on left side of a panel and the other stages of the plurality of stages are disposed on right side of the panel,
wherein each of the stages comprises: -
a driving unit which charges to a predetermined voltage in response to one of an output start signal and an output signal of a previous stage, and which generates the output signal in response to any one of the clock signals; and a discharge unit which discharges the predetermined voltage in response to an output signal of a next stage, wherein the driving unit comprises; an input unit which outputs a first voltage in response to one of the output start signal and an output signal of the previous stage; and an output unit which charges to the first voltage and generates the output signal in response to any one of the clock signals, wherein some stages disposed on left side of the panel and the other stages disposed on right side of the panel are alternatively connected to gate lines, wherein each of the clock signals having a duty ratio of less than 50% and a different phase from each of the other clock signals, wherein the output signal of the output unit is transmitted to a gate line and the next stage, and wherein the clock signals for some stages disposed on left side of the panel or the other stages disposed on right side of the panel have high value with a frequency of every 4 horizontal periods. - View Dependent Claims (16)
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17. A shift register comprising a plurality of stages, wherein stages of the plurality of stages are connected to each other and a current (N-th) stage thereof generates an output signal in response to any one of a plurality of clock signals and an output from each of two different stages thereof, each of the clock signals having a duty ratio of less than 50% and a different phase from each of the other clock signals,
wherein each of the stages comprises: -
a driving unit which charges to a predetermined voltage in response to one of an output start signal and an output signal of a previous stage, the previous stage being disposed two stages previous (N−
2) to the current stage, and which generates the output signal in response to any one of the clock signals; anda discharge unit which discharges the predetermined voltage in response to an output signal of a next stage, the next stage being disposed two stages after (N+2) the current stage, wherein the driving unit comprises; an input unit which outputs a first voltage in response to one of the output start signal and an output signal of the previous (N−
2) stage; andan output unit which charges to the first voltage and generates the output signal in response to any one of the clock signals, wherein the output unit comprises two output circuits having substantially a same structure, and wherein each of the stages further comprises an output assistant unit transmitting the first voltage to the output unit in response to an output of the input unit. - View Dependent Claims (18, 19, 20, 21)
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Specification