Wear leveling method and controller using the same

• US 8,108,589 B2
• Filed: 01/22/2008
• Issued: 01/31/2012
• Est. Priority Date: 10/04/2007
• Status: Active Grant

• Current Assignee: Emtops Electronics Corp. (Phison Electronics Corporation)
• Original Assignee: Phison Electronics Corporation
• Inventors: Yeh, Chih-Kang, Chu, Chien-Hua
• Primary Examiner(s): Bragdon, Reginald
• Assistant Examiner(s): SADLER, NATHAN
• Application Number:
  US12/017,550
• Publication Number:
  US 20090094409A1
• Time in Patent Office: 1,470 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A wear leveling method for non-volatile memory is provided, by which the non-volatile memory is substantially divided into a plurality of blocks and the blocks are grouped into a data area and a spare area. The method includes selecting a block based on an erased sequence when getting the block from the spare area. The method also includes performing a wear leveling procedure.

Claims

1. A wear leveling method for a non-volatile memory, wherein the non-volatile memory is substantially divided into a plurality of physical blocks, and the physical blocks are at least grouped into a data area, a spare area and a temporary area, the wear leveling method comprising:

recording a plurality of erased physical blocks in an erased block table based on an erased sequence of the erased physical blocks, wherein the erased physical blocks are recorded without a weight mark or with the weight mark;

when a target physical block is about to be selected from the spare area, judging whether the target physical block is used for the data area or the temporary area;

selecting a physical block with the weight mark and being primarily erased among the physical blocks of the spare area to be the target physical block based on the erased sequence in the erased block table when the target physical block is used for the data area;

selecting a physical block without the weight mark and being lastly erased within the spare area to be the target physical block based on the erased sequence in the erased block table when the target physical block is used for the temporary area; and

performing a wear leveling procedure.

2. The wear leveling method for a non-volatile memory as claimed in claim 1, wherein the wear leveling procedure comprises:

exchanging the physical block mapping to an unused logical block with the physical block with the weight mark within the spare area.

3. The wear leveling method for a non-volatile memory as claimed in claim 2 further comprising:

recording utilization information of a logical block by using a logical physical mapping table.

4. The wear leveling method for a non-volatile memory as claimed in claim 1, wherein the step of performing the wear leveling procedure is executed whenever performing the erasing of the physical blocks for a first predetermined erasing times.

5. The wear leveling method for a non-volatile memory as claimed in claim 1, wherein the step of performing the wear leveling procedure is executed in a random mode.

6. The wear leveling method for a non-volatile memory as claimed in claim 1, wherein the erased physical block is not recorded if the erased physical block has been recorded in the erased block table for a second predetermined times.

7. The wear leveling method for a non-volatile memory as claimed in claim 6 further comprising:

if there is no record within the erased block table, selecting the physical block from the spare area in the random mode or the sequential mode when the physical block is selected from the spare area.

8. The wear leveling method for a non-volatile memory as claimed in claim 1, wherein the step of recording the erased physical blocks in the erased block table based on the erased sequence of the erased physical blocks comprising:

recording the erased physical blocks according to a circular coverage mode, wherein if the erased physical block repeatedly recorded in the erased block table is about to be overwritten, a primary record of other erasing records of the erased physical block within the erased block table is then marked with the weight mark.

9. The wear leveling method for a non-volatile memory as claimed in claim 1, wherein the step of selecting the physical block with the weight mark and being primarily erased within the spare area based on the erased sequence in the erased block table when the physical block is used for the data area comprises:

judging whether the physical block with the weight mark exists in the spare area, and selecting a primarily erased physical block within the spare area based on the erased sequence in the erased block table if there is no physical block with the weight mark.

10. The wear leveling method for a non-volatile memory as claimed in claim 1, wherein the step of selecting the physical block based on an erased sequence of the erased physical blocks recorded in the erased block table and the usage further comprising:

selecting the physical block from the spare area in a random mode or a sequential mode when the physical block is selected from the spare area and is used for a substitute area further grouped according to the physical blocks.

11. The wear leveling method for a non-volatile memory as claimed in claim 1, wherein the step of performing the wear leveling procedure is executed by a normal writing instruction of a host.

12. A controller, for a storage device, wherein a non-volatile memory of the storage device is substantially divided into a plurality of physical blocks, and the physical blocks are at least grouped into a data area and a spare area, the controller comprising:

a microprocessor unit is configured for controlling a whole operation of the controller;

a buffer memory is electrically connected to the microprocessor unit and configured for temporarily storing data;

a non-volatile memory interface is electrically connected to the microprocessor unit and configured for accessing the non-volatile memory; and

a memory management module is electrically connected to the microprocessor unit and configured for managing the non-volatile memory, wherein the memory management module records a plurality of erased physical blocks in an erased block table based on the erased sequence of the erased physical blocks, wherein the erased physical blocks are recorded without a weight mark or with the weight mark,

wherein when a target physical block is about to be selected from the spare area, the memory management module judges whether the target physical block is used for the data area or the temporary area,

wherein the memory management module selects a physical block with the weight mark and being primarily erased among the physical blocks of the spare area to be the target physical block based on the erased sequence in the erased block table when the target physical block is used for the data area,

wherein the memory management module selects a physical block without the weight mark and being lastly erased among the physical blocks of the spare area to be the target physical block based on the erased sequence in the erased block table when the target physical block is used for the temporary area,

wherein the memory management module exchanges the physical block in the spare area with a physical block in the data area.

13. The controller as claimed in claim 12, wherein the memory management module exchanges the physical block mapping to an unused logical block with the physical block with the weight mark within the spare area.

14. The controller as claimed in claim 13, wherein the memory management module further records utilization information of a logical block by using a logical physical mapping table.

15. The controller as claimed in claim 12, wherein the memory management module exchanges the physical block in the spare area with the physical block in the data area whenever the memory management module performs the erasing of the physical blocks for a first predetermined erasing times.

16. The controller as claimed in claim 12, wherein the memory management module exchanges the physical block in the spare area with the physical block in the data area in a random mode.

17. The controller as claimed in claim 12, wherein the erased physical block is not recorded if the erased physical block has been recorded in the erased block table for a second predetermined times.

18. The controller as claimed in claim 17, wherein if there is no record within the erased block table, the memory management module selects the physical block from the spare area in the random mode or the sequential mode when the physical block is selected from the spare area.

19. The controller as claimed in claim 12, wherein the memory management module further records the erased physical block in the erased block table according to a circular coverage mode, wherein if the erased physical block repeatedly recorded in the erased block table is about to be overwritten, a primary record of other erasing records of the erased physical block within the erased block table is then marked with the weight mark.

20. The controller as claimed in claim 12, wherein the memory management module further judges whether the physical block with the weight mark exists in the spare area, and selects a primarily erased physical block within the spare area based on the erased sequence in the erased block table if there is no physical block with the weight mark.

21. The controller as claimed in claim 12, wherein the memory management module further selects the physical block from the spare area in a random mode or a sequential mode when the physical block is selected from the spare area and is used for a substitute area further grouped according to the physical blocks.

22. The controller as claimed in claim 12, wherein the memory management module further exchanges the physical block in the spare area with the physical block in the data area by executing a normal writing instruction of a host.

23. The controller as claimed in claim 12, wherein the non-volatile memory is a SLC NAND flash memory or a MLC NAND flash memory.