Multi-operation write aggregator using a page buffer and a scratch flash block in each of multiple channels of a large array of flash memory to reduce block wear

• US 8,108,590 B2
• Filed: 06/16/2008
• Issued: 01/31/2012
• Est. Priority Date: 01/06/2000
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Chow, David Q., Yu, Frank, Lee, Charles C., Ma, Abraham C., Shen, Ming-Shiang
• Primary Examiner(s): KROFCHECK, MICHAEL C
• Application Number:
  US12/139,842
• Publication Number:
  US 20080250195A1
• Time in Patent Office: 1,324 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 21/32 using biometric data, e.g. fingerprints, iris scans or voiceprints
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06K 19/07 with integrated circuit chips
• CPC Class Codes: G06K 19/07354 by biometrically sensitive means, e.g. fingerprint sensitive fingerprint sensors in general G06V40/12; biometrically activated access control G07C9/25

Abstract

A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA'"'"'s) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB'"'"'s, which are tracked by an AFB tracking table.

Claims

1. A multi-channel fragment-accumulating flash-memory system comprising:

a multi-channel controller processor coupled to receive host data and a host address;

a plurality of channels of flash memory coupled to the multi-channel controller processor;

a plurality of Aggregating Flash Blocks (AFBs), including an AFB in each channel of the flash memory, the AFB being a physical block of the flash memory assigned for aggregating data fragments;

a page buffer for each channel that accumulates a page of the host data before writing to the flash memory;

an AFB tracking table having entries for the plurality of AFBs, an entry storing a physical block number that locates the AFB within the flash memory, a data valid flag indicating when the AFB is storing valid data, and a stored logical address;

a multi-AFB manager that compares the host address to the stored logical address in entries in the AFB tracking table to locate a matching entry in the AFB tracking table, the multi-AFB manager assigning an assigned AFB pointed to by the physical block number of the matching entry;

a combining process executed by the multi-channel controller processor when a page boundary of the page buffer is reached, the matching entry in the AFB tracking table is found by the multi-AFB manager, and the page buffer is not full, the combining process copying the host data in the page buffer and a data fragment read from the assigned AFB to a target physical block in the flash memory,

whereby the data fragment stored in the assigned AFB is combined with the host data in the page buffer when writing to the target physical block.

2. The multi-channel fragment-accumulating flash-memory system of claim 1 further comprising:

a flush process executed by the multi-channel controller processor when a page boundary of the page buffer is reached, that copies the host data in the page buffer to a target physical block in the flash memory; and

a STOP process executed by the multi-channel controller processor when a STOP command is received from a host, that copies the host data in the page buffer to a newly assigned AFB in the flash memory, and for updating the AFB tracking table for the newly assigned AFB.

3. The multi-channel fragment-accumulating flash-memory system of claim 2 wherein the AFB and the target physical block are both in a same channel of the flash memory,

whereby fragment aggregation is performed on a per-channel basis.

4. The multi-channel fragment-accumulating flash-memory system of claim 3 wherein a page-size of the flash memory is a minimum amount of data that the flash memory is able to read;

wherein a block-size of the flash memory is a minimum amount of data that the flash memory is able to erase;

wherein the page buffer stores a page-size of data;

wherein the AFB and the target physical block each store a block-size of data;

wherein the block-size is at least 8 times the page-size;

wherein the page size is at least 1K bytes.

5. The multi-channel fragment-accumulating flash-memory system of claim 2 further comprising:

a single package, a single chip, or a multi-chip package that contains one or more of the plurality of channels of flash memory and the multi-channel controller processor.

6. The multi-channel fragment-accumulating flash-memory system of claim 2 further comprising:

an address correlation and page usage memory (ACPUM) that stores partial logical-to-physical address and page usage information (PLTPPUI) that indicate the target physical block corresponding to the host address,

whereby the target physical block is located by looking up the host address in the ACPUM.

7. The multi-channel fragment-accumulating flash-memory system of claim 2 wherein the entry in the AFB tracking table also stores a last page number that locates valid data within the AFB pointed to by the physical block number of the entry.

8. A computer-implemented method for reducing wear of flash memory by aggregating writes in an Aggregating Flash Block (AFB) comprising:

receiving a host-write request from a host;

assigning the host-write request to an assigned channel of the flash memory;

storing host data from the host in a page buffer for the assigned channel;

comparing a host address from the host to a plurality of stored logical addresses for a plurality of Aggregating Flash Blocks (AFBs) in the flash memory to find a matching entry;

when no matching entry is found and a page boundary is reached in the page buffer, copying host data in the page buffer to a target physical block in the flash memory;

when the matching entry is found and a page boundary is reached in the page buffer, and the page buffer is full, copying host data in the page buffer to the target physical block in the flash memory; and

when the matching entry is found and a page boundary is reached in the page buffer, and the page buffer is not full, copying host data in the page buffer to the target physical block in the flash memory and copying old data fragments in the AFB to the target physical block to combine host data with old data fragments to reduce data fragments,

whereby host data is combined with old data fragments in the AFB to reduce wear due to additional data fragments.

9. The computer-implemented method of claim 8 further comprising:

setting sector update flags to indicate valid data in the page buffer;

using the sector update flags to locate valid data in the page buffer for copying to the target physical block,

whereby sector update flags locate valid data in the page buffer.

10. The computer-implemented method of claim 8 further comprising:

when a stop command is received from the host, selecting a new AFB and copying host data in the page buffer to the new AFB in the flash memory.

11. The computer-implemented method of claim 10 further comprising:

reading the plurality of stored logical addresses from an AFB tracking table that has entries for each of the AFBs; and

updating the AFB tracking table when the new AFB is selected.

12. The computer-implemented method of claim 11 wherein selecting the new AFB comprises for each entry in the AFB tracking table:

reading a data valid flag from the entry and skipping to a next entry in the AFB tracking table when the data valid flag is valid;

reading a status of a flash memory chip pointed to by the entry and skipping to the next entry in the AFB tracking table when the status is busy;

assigning an AFB pointed to by the entry as the new AFB when the data valid flag is not valid and the status is not busy; and

assigning an AFB pointed to by a last entry in the AFB tracking table as the new AFB when no entry has the data valid flag not valid and the status not busy.

13. The computer-implemented method of claim 12 further comprising:

when no entry has the data valid flag not valid and the status not busy;

copying valid data in a first AFB pointed to by a first entry to a target physical block in the flash memory;

deleting the first entry in the AFB tracking table; and

moving entries in the AFB tracking table up by one entry position.

14. The computer-implemented method of claim 8 further comprising:

updating an address correlation and page usage memory (ACPUM) when host data is written to the flash memory to track valid pages in the flash memory.

15. The computer-implemented method of claim 14 further comprising:

when the address correlation and page usage memory (ACPUM) does not contain a partial logical-to-physical address and page usage information (PLTPPUI) for the host address, loading a corresponding partial logical-to-physical address and page usage information (PLTPPUI) from a PLTPPUI tracking table; and

reading an address of the target physical block from the PLTPPUI in the ACPUM.

16. A page-accumulating and block-aggregating flash system comprising:

a multi-channel controller coupled to receive host data and a host address;

a plurality of channels of flash memory coupled to the multi-channel controller;

a plurality of Aggregating Flash Blocks (AFBs), including an AFB in each channel of the flash memory, the AFB being a physical block of the flash memory assigned for aggregating old data fragments;

a page buffer for each channel that accumulates a page of the host data before writing to the flash memory;

an AFB tracking table that stores entries for each of the plurality of AFBs, the AFB tracking table having a plurality of stored logical addresses for old data fragments stored in the plurality of AFBs and a plurality of physical block numbers that locate the plurality of AFBs within the flash memory;

compare means, reading the plurality of stored logical addresses from the AFB tracking table, for comparing the host address to the plurality of stored logical addresses to find a matching entry in the AFB tracking table;

a non-combining buffer-flush process, activated when no matching entry is found and a page boundary is reached in the page buffer, and also activated when the matching entry is found and a page boundary is reached in the page buffer, and the page buffer is full, that copies host data in the page buffer to a target physical block in the flash memory; and

a combining buffer-flush process, activated when the matching entry is found and a page boundary is reached in the page buffer, and the page buffer is not full, that copies host data in the page buffer to the target physical block in the flash memory and copies old data fragments in the AFB to the target physical block to combine host data with old data fragments to reduce old data fragments,

whereby old data fragments are accumulated in the AFB and combined with accumulated host data when flushing the page buffer to the flash memory.

17. The page-accumulating and block-aggregating flash system of claim 16 wherein the old data fragments in the AFBs are stored in non-volatile flash memory while the host data accumulated in the page buffer is stored in a volatile memory.

18. The page-accumulating and block-aggregating flash system of claim 16 further comprising:

a flush process, activated when a page boundary of the page buffer is reached, that copies the host data in the page buffer to a target physical block in the flash memory.

19. The page-accumulating and block-aggregating flash system of claim 16 further comprising:

STOP process means, activated when a STOP command is received from a host, for copying the host data in the page buffer to a newly assigned AFB in the flash memory, and for updating the AFB tracking table for the newly assigned AFB.

20. The page-accumulating and block-aggregating flash system of claim 16 further comprising:

address correlation and page usage memory (ACPUM) means for storing partial logical-to-physical address and page usage information (PLTPPUI) that indicates the target physical block corresponding to the host address,

whereby the target physical block is located by looking up the host address in the ACPUM means.

21. The page-accumulating and block-aggregating flash system of claim 16 wherein each of the plurality of channels of flash memory further comprises:

a single package, a single chip, or a multi-chip package;

wherein each channel of flash memory is packaged in a single package, a single chip, or a multi-chip package.