Optimizing non-preemptible read-copy update for low-power usage by avoiding unnecessary wakeups
First Claim
1. A method for low-power detection of a grace period following a shared data element update operation that affects non-preemptible data readers, comprising:
- implementing a grace period processing action that requires a processor that may be running a non-preemptible reader of said shared data element to pass through a quiescent state before further grace period processing can proceed, said quiescent state ensuring that said reader will not be affected by said further grace period processing;
determining a power status of said processor; and
proceeding with said further grace period processing without requiring said processor to pass through said quiescent state based solely on said power status indicating that quiescent state processing by said processor is unnecessary.
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Abstract
A technique for low-power detection of a grace period following a shared data element update operation that affects non-preemptible data readers. A grace period processing action is implemented that requires a processor that may be running a non-preemptible reader of the shared data element to pass through a quiescent state before further grace period processing can proceed. A power status of the processor is also determined. Further grace period processing may proceed without requiring the processor to pass through a quiescent state if the power status indicates that quiescent state processing by the processor is unnecessary.
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Citations
20 Claims
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1. A method for low-power detection of a grace period following a shared data element update operation that affects non-preemptible data readers, comprising:
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implementing a grace period processing action that requires a processor that may be running a non-preemptible reader of said shared data element to pass through a quiescent state before further grace period processing can proceed, said quiescent state ensuring that said reader will not be affected by said further grace period processing; determining a power status of said processor; and proceeding with said further grace period processing without requiring said processor to pass through said quiescent state based solely on said power status indicating that quiescent state processing by said processor is unnecessary. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A system adapted for low-power detection of a grace period following a shared data element update operation that affects non-preemptible data readers, comprising:
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one or more processors; a memory coupled to said one or more processors, said memory including a computer useable medium tangibly embodying at least one program of instructions executable by said processor to perform operations, comprising; implementing a grace period processing action that requires a processor that may be running a non-preemptible reader of said shared data element to pass through a quiescent state before further grace period processing can proceed, said quiescent state ensuring that said reader will not be affected by said further grace period processing; determining a power status of said processor; and proceeding with said further grace period processing without requiring said processor to pass through said quiescent state based solely on said power status indicating that quiescent state processing by said processor is unnecessary. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A computer program product for low-power detection of a grace period following a shared data element update operation that affects non-preemptible data readers, comprising:
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one or more machine-useable non-transitory media; logic provided by said one or more media for programming a data processing platform to operate as by; implementing a grace period processing action that requires a processor that may be running a non-preemptible reader of said shared data element to pass through a quiescent state before further grace period processing can proceed, said quiescent state ensuring that said reader will not be affected by said further grace period processing; determining a power status of said processor; and proceeding with said further grace period processing without requiring said processor to pass through said quiescent state based solely on said power status indicating that quiescent state processing by said processor is unnecessary. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A computer program product for low-power detection of a grace period following a shared data element update that affects non-preemptible data readers, comprising:
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one or more machine-useable non-transitory media; logic provided by said one or more media for programming a data processing platform to operate as by; implementing a grace period processing action that requires a processor that may be running a non-preemptible reader of said shared data element to pass through a quiescent state before further grace period processing can proceed, said quiescent state ensuring that said reader will not be affected by said further grace period processing; determining a power status of said processor; and proceeding with said further grace period processing without requiring said processor to pass through said quiescent state based solely on said power status indicating that quiescent state processing by said processor is unnecessary; said power status comprising said processor being in either a non-low-power state or a low-power state; said low-power state including said processor being in a dynamic tick timer mode; said power status is determined by a current power state of said processor and said processor is designated as having passed through said quiescent state if said current power state is a low-power state; and said power status being determined from a power status indicator that is manipulated by said processor when said processor enters or leaves a low-power state. - View Dependent Claims (20)
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Specification