Method and apparatus for selectively compacting test responses
First Claim
1. A method, comprising:
- receiving test response values generated during testing of an integrated circuit, the test response values being responsive to deterministic test patterns applied to the integrated circuit;
masking one or more of the test response values before the one or more of the test response values are input into one or more compactors, the one or more masked test response values including one or more unknown test response values or one or more test response values showing a fault effect, at least one of the one or more compactors comprising a feedback-free network of XOR or XNOR gates; and
compacting the test response values, including the one or more masked test response values, in the one or more compactors.
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Abstract
A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.
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Citations
17 Claims
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1. A method, comprising:
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receiving test response values generated during testing of an integrated circuit, the test response values being responsive to deterministic test patterns applied to the integrated circuit; masking one or more of the test response values before the one or more of the test response values are input into one or more compactors, the one or more masked test response values including one or more unknown test response values or one or more test response values showing a fault effect, at least one of the one or more compactors comprising a feedback-free network of XOR or XNOR gates; and compacting the test response values, including the one or more masked test response values, in the one or more compactors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system, comprising:
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means for masking one or more test response values generated during testing of an integrated circuit before the one or more test response values are compacted, the test response values being responsive to deterministic test patterns applied to the integrated circuit, the one or more masked test response values including one or more unknown test response values or one or more test response values showing a fault effect; and means for compacting the test response values, including the one or more masked test response values, the means for compacting the test response values comprising a feedback-free network of XOR or XNOR gates. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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Specification