Planar SRFET using no additional masks and layout method

• US 8,110,869 B2
• Filed: 10/01/2007
• Issued: 02/07/2012
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US11/906,476
• Publication Number:
  US 20080029812A1
• Time in Patent Office: 1,590 Days
• Field of Search: 257328-335
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A semiconductor power device supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer with a same conductivity type as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region of a second conductivity type extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region of second conductivity type. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode.

Claims

1. A semiconductor power device supported on a semiconductor substrate of a first conductivity type having a bottom layer functioning as a bottom electrode and an epitaxial layer overlying said bottom layer having a same conductivity type as said bottom layer, said semiconductor power device comprising:

a plurality of FET cells wherein each FET cell further comprises a body region of a second conductivity type extending vertically from a top surface into said epitaxial layer and laterally surrounding outer edges of each of the FET cells underneath a planar insulated gate disposed substantially in a central portion of the FET cell on the top surface of the semiconductor substrate;

each of said FET cells further includes a source region of the first conductivity type encompassed in said body region immediately under and laterally surrounding outer edges of said planar insulated gate;

each of said FET cells further includes a heavy body dopant region of said second conductivity type encompassed in said body region and disposed underneath and extends outwardly toward and terminates before reaching the outer edges of the FET cells thus forming a Schottky pocket near the top surface of the semiconductor substrate in said body region;

a Schottky metal layer disposed on the top surface of the epitaxial layer extends laterally from an outer edges of the source region across an area of the top surface of the semiconductor substrate over the heavy body dopant region and the Schottky pocket in of the body region near the top surface of the semiconductor substrate surrounding the heavy body dopant region, wherein said Schottky metal layer further extending over an area on the top surface of the semiconductor substrate across an open substrate region between two of said FET cells and then further extends to the outer edge of the source region of another FET cell thus forming an integrated Schottky junction diode for the FET cells; and

each of said FET cells further comprises a closed FET cell.

2. The semiconductor power device of claim 1 wherein:

the Schottky metal layer further comprises a Ti/TiN layer.