Semiconductor device with transistor, conductive pad, and contact

• US 8,110,872 B2
• Filed: 11/18/2009
• Issued: 02/07/2012
• Est. Priority Date: 11/19/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Fujimoto, Hiroyuki
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US12/621,104
• Publication Number:
  US 20100123170A1
• Time in Patent Office: 811 Days
• Field of Search: 257/330, 257/E27.062, 257/E29.267
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A semiconductor device includes a transistor, a conductive pad, and a contact. The conductive pad is electrically connected to the transistor. The conductive pad may include, but is not limited to, a first region and a second region. The contact is electrically connected to the conductive pad. At least a main part of the first region overlaps the transistor in plan view. At least a main part of the second region does not overlap the transistor in plan view. At least a main part of the contact overlaps the second region in plan view. The at least main part of the contact does not overlap the first region in plan view. The at least main part of the contact does not overlap the transistor in plan view.

Claims

1. A semiconductor device comprising:

a transistor;

a conductive pad being electrically connected to the transistor, the conductive pad comprising a first region and a second region;

a contact being electrically connected to the conductive pad, wherein at least a main part of the first region overlaps the transistor in plan view, at least a main part of the second region does not overlap the transistor in plan view, at least a main part of the contact overlaps the second region in plan view, the at least main part of the contact does not overlap the first region in plan view, and the at least main part of the contact does not overlap the transistor in plan view; and

a pad contact layer disposed between an upper diffusion layer of the transistor and the first region of the conductive pad,

wherein the pad contact layer overlaps the upper diffusion layer and the first region of the conductive pad in plan view, and

the pad contact layer reduces a contact resistance between the upper diffusion layer and the first region of the conductive pad.

2. The semiconductor device according to claim 1, further comprising:

a capacitor disposed over the contact, the capacitor being electrically connected to the contact.

3. The semiconductor device according to claim 1, wherein plural sets of the transistor, the conductive pad and the contact are provided,

the transistors are disposed in a form of a matrix array, and

pairs of the conductive pads and the contacts are disposed in a form of a staggered array.

4. The semiconductor device according to claim 1, wherein plural sets of the transistor, the conductive pad and the contact are disposed in a form of a matrix array.

5. A semiconductor device comprising:

a transistor;

a conductive pad being electrically connected to the transistor, the conductive pad comprising a first region and a second region;

a contact being electrically connected to the conductive pad, wherein at least a main part of the first region overlaps the transistor in plan view, at least a main part of the second region does not overlap the transistor in plan view, at least a main part of the contact overlaps the second region in plan view, the at least main part of the contact does not overlap the first region in plan view, and the at least main part of the contact does not overlap the transistor in plan view; and

a metal layer disposed between the contact and the second region of the conductive pad,

wherein the conductive pad comprises a silicide layer.

6. The semiconductor device according to claim 5, wherein the transistor comprises:

a lower diffusion layer;

a pillar disposed over the lower diffusion layer;

an upper diffusion layer disposed over the pillar, the upper diffusion layer being connected to the first region of the conductive pad.

7. The semiconductor device according to claim 5, further comprising:

a capacitor disposed over the contact, the capacitor being electrically connected to the contact.

8. The semiconductor device according to claim 5, wherein plural sets of the transistor, the conductive pad and the contact are provided,

the transistors are disposed in a form of a matrix array, and

pairs of the conductive pads and the contacts are disposed in a form of a staggered array.

9. The semiconductor device according to claim 5, wherein plural sets of the transistor, the conductive pad and the contact are disposed in a form of a matrix array.

10. A semiconductor device comprising:

a semiconductor body;

a plurality of semiconductor pillars projecting from the semiconductor body with a space thereamong, each of the semiconductor pillars comprising a first diffusion region formed in an upper portion thereof, a second diffusion region formed in a lower portion thereof and a channel region formed in a portion between the upper and lower portions, the semiconductor pillars including a first semiconductor pillar;

a conductive pad comprising first and second regions, the first region being in contact with the first diffusion region of the first semiconductor pillar, the second region being elongated laterally from the first region and terminating over the space; and

a contact formed in contact with the second region of the conductive pad so that a contacting portion between the contact and the second region of the conductive pad lies in plan view apart from the first region of the conductive pad and from the first region of each of the semiconductor pillars inclusive of the first semiconductor pillar.

11. The device as claimed in claim 10, wherein the conductive pad comprises a polycrystalline semiconductor layer and the contact comprises a metal layer.

12. The device as claimed in claim 10, further comprising:

a plurality of additional conductive pads each comprising first and second regions, the first region of each of the additional conductive pads being, in contact with the first diffusion region of an associated one of remaining ones of the semiconductor pillars, the second region of each of the additional conductive pads being elongated laterally from the first region of an associated one of the additional conductive pads and terminating over the space; and

a plurality of additional contacts each formed in contact with the second region of an associated one of the additional conductive pads so that a contacting portion between each of the additional contacts and the second region of each of the additional conductive pads lies in plan view apart from the first region of each of the additional conductive pads and from the first diffusion region of each of the semiconductor pillars inclusive of the first semiconductor pillar.

13. The device as claimed in claim 12, wherein the device further comprises a plurality of capacitors that are electrically connected respectively to the contact and the additional contacts.

14. The device as claimed in claim 12, wherein the semiconductor pillars inclusive of the first semiconductor pillar are arranged in matrix including a plurality of rows and columns, the second regions belonging to the same column are disposed in line, and the second regions belonging to the same row are disposed in zigzag.

15. The device as claimed in claim 14, wherein the device further comprises a plurality of capacitors that are electrically connected respectively to the contact and the additional contacts.

16. The device as claimed in claim 10, wherein the space is filled with gate structures and an insulating layer, each of the gate structures includes a gate insulating film covering the channel region of an associated one of the semiconductor pillars inclusive of the first semiconductor pillar and a gate electrode formed on the gate insulating film, the insulating layer being between adjacent ones of the gate electrodes.

17. The device as claimed in claim 16, wherein the semiconductor pillars inclusive of the first semiconductor pillar are arranged in matrix including a plurality of rows and columns, the gate electrodes of adjacent ones of the gate structures belonging to the same column are in contact with each other, and the insulating layer intervenes between the gate electrodes of adjacent ones of the gate structures belonging to the same row.

18. The device as claimed in claim 17, wherein the device further comprises a plurality of capacitors that are electrically connected respectively to the contact and the additional contacts.