Chip package and manufacturing method thereof

• US 8,110,902 B2
• Filed: 02/19/2009
• Issued: 02/07/2012
• Est. Priority Date: 02/19/2009
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Eun, Younghyo, Kim, Dukman
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US12/388,761
• Publication Number:
  US 20100207258A1
• Time in Patent Office: 1,083 Days
• Field of Search: 257/659, 257/660, 257/687, 257/691, 257/692, 257/787, 257/E21.499, 257/E23.114
• US Class Current: 257/659
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/055 the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A chip package including at least a shielding layer for better electromagnetic interferences shielding is provided. The shielding layer disposed over the top surface of the laminate substrate can protect the chip package from the underneath EMI radiation. The chip package may further include another shielding layer over the molding compound of the chip package.

Claims

1. A chip package, comprising:

a substrate having a plurality of contacts, a die pad, and a ground path;

a chip disposed on the die pad;

a first shielding layer;

a package body encapsulating the chip and a portion of the first shielding layer; and

a second shielding layer disposed over the package body;

wherein;

the first shielding layer defines a plurality of first openings that expose the contacts; and

the first shielding layer substantially covers a first surface of the substrate wherein the first shielding layer is substantially planar.

2. The chip package as chinned in claim 1, wherein the plurality of first openings are larger than the correspondingly exposed contacts.

3. The chin package as claimed in claim 1, wherein:

the first shielding layer defines a second opening exposing the die pad.

4. The chip package as claimed in claim 3, wherein the second opening is at least as large as the die pad.

5. The chip package as claimed in claim 1, wherein:

the first shielding layer and the second shielding layer are electrically connected to the ground path; and

the ground path comprises at least one ground via.

6. The chip package as claimed in claim 5, wherein the first shielding layer covers the ground via of the substrate.

7. The chip package as claimed in claim 1, wherein:

a material of the first shielding layer is a solder material; and

a material of the second shielding layer is a solder material.

8. The chip package as claimed in claim 1, wherein the second shielding layer conformally covers the package body.

9. A chip package, comprising:

a substrate having a top surface and a back surface opposite the top surface;

a plurality of contacts disposed on the top surface of the substrate;

a chip disposed on the top surface of the substrate;

a first shielding layer disposed over the top surface of the substrate and having a plurality of first openings, wherein each of the plurality of openings circumscribes and exposes a corresponding one of the plurality of contacts;

a molding compound encapsulating a portion of the first shielding layer; and

a second shielding layer disposed over an exterior surface of the molding compound.

10. The chip package as claimed in claim 9, wherein the substrate further has a ground via, and the first shielding layer is electrically connected to the ground via.

11. The chip package as claimed in claim 9, wherein the first shielding layer substantially covers the top surface of the substrate while exposing the contacts.

12. The chip package as claimed in claim 9, wherein the first shielding layer is substantially planar.

13. The chip package as claimed in claim 9, wherein:

the first shielding layer defines a second opening that exposes the chip; and

the first shielding layer substantially covers the top surface of the substrate while exposing the contacts and the chip.

14. A chip package, comprising:

a substrate having a ground path, a top surface, and a back surface opposite to the top surface;

a plurality of contacts disposed adjacent to the top surface of the substrate;

a chip disposed on the top surface of the substrate;

a first shielding layer;

disposed over the top surface of the substrate;

circumscribing and exposing the contacts and the chip; and

disposed between the chip and at least one of the contacts;

a molding compound encapsulating a portion of the first shielding layer; and

a second shielding layer disposed over the molding compound;

wherein the first shielding layer and the second shielding layer are electrically connected to the ground path wherein the first shielding layer defines a plurality of openings, wherein each of the plurality of openings circumscribes and exposes a corresponding one of the contacts.

15. The chip package as claimed in claim 14, wherein the first shielding layer is substantially planar.

16. The chip package as claimed in claim 14, wherein the ground path includes a ground via and the ground via, the first shielding layer, and the second shielding layer form a common ground.

17. A chip package, comprising:

a substrate having a ground path, a top surface, and a back surface opposite to the top surface;

a plurality of contacts disposed adjacent to the top surface of the substrate;

a first shielding layer;

disposed over the top surface of the substrate;

circumscribing and exposing the contacts and the chip; and

disposed between the chip and at least one of the contacts;

a molding compound encapsulating a portion of the first shielding layer; and

a second shielding layer disposed over the molding compound;

wherein the first shielding layer and the second shielding layer are electrically connected to the ground path,

wherein the first shielding layer substantially covers the top surface of the substrate while exposing the contacts and the chip.

18. A chip package, comprising:

a substrate having a plurality of contacts, a die pad, and a ground path;

a chip disposed on the die pad;

a first shielding layer;

a package body encapsulating the chip and a portion of the first shielding layer; and

a second shielding layer disposed over the package body;

wherein;

the first shielding layer defines a plurality of first openings that expose the contacts; and

the first shielding layer substantially covers a first surface of the substrate,

wherein each of the plurality of openings circumscribes a corresponding one of the contacts.