Liquid crystal display device and fabricating method thereof

• US 8,111,363 B2
• Filed: 11/22/2010
• Issued: 02/07/2012
• Est. Priority Date: 12/24/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Ahn, Byung Chul
• Primary Examiner(s): Robinson, Mark
• Assistant Examiner(s): INADOMI, MICHAEL J
• Application Number:
  US12/951,907
• Publication Number:
  US 20110063556A1
• Time in Patent Office: 442 Days
• Field of Search: 349/141
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/13629 Multilayer wirings

Abstract

A LCD device includes a gate line on a substrate and a data line crossing the gate line to define a pixel area; a thin film transistor source and drain electrodes; a common line parallel to the gate line; a common electrode extended from the common line and a pixel electrode extending from the drain electrode wherein the gate line and the common line have a first conductive layer group having at least double conductive layers, and the common electrode is formed by an extension of at least one transparent conductive layer of the common line; and the gate line, the source electrode and the drain electrode have a second conductive layer group having at least double conductive layers, and the pixel electrode is formed by an extension of at least one transparent conductive layer of the drain electrode.

Claims

1. A liquid crystal display device, comprising:

a gate line on a substrate;

a data line crossing the gate line with a gate insulating film therebetween, wherein the data and gate lines define a pixel area;

a thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode opposed to the source electrode and a semiconductor pattern defining a channel between the source electrode and the drain electrode;

a common line on the substrate and substantially parallel to the gate line;

a common electrode extended from the common line into the pixel area; and

a pixel electrode extended from the drain electrode into the pixel area to form a horizontal electric field with the common electrode by the pixel electrode being parallel to the common electrode,

wherein the gate line and the common line have a first conductive layer group having at least double conductive layers which have a lowermost layer of a transparent conductive material and an upper conductive layer of a metal material, and the common electrode is formed by an extension of the lowermost layer of the transparent conductive material of the common line; and

the data line, the source electrode and the drain electrode have a second conductive layer group having at least double conductive layers which have a lowermost layer of a transparent conductive material and an upper conductive layer of a metal material, and the pixel electrode is formed by an extension of the lowermost layer of the transparent conductive material of the drain electrode.

2. The device as claimed in claim 1, further comprising:

a storage capacitor provided by an overlap of the drain electrode with a portion of the common electrode and the gate insulating film therebetween.

3. The device as claimed in claim 1, wherein the lowermost transparent conductive layers of the common electrode and the pixel electrode of the first and second conductive layer group includes at least one of ITO, TO, IZO and ITZO.

4. The device as claimed in claim 3, wherein the upper conductive layer of metal material of the first and second conductive layer groups have at least one of a single layer structure and at least a double layer structure of Mo, Ti, Cu, AlNd, Al, Cr, a Mo-alloy, a Cu-alloy and an Al-alloy.

5. The device as claimed in claim 4, further comprising:

a gate pad connected to the gate line;

a data pad connected to the data link; and

a common pad connected the common line,

wherein each of the gate pad, the data pad and the common pad is formed of the first conductive layer group.

6. The device as claimed in claim 5, wherein each of the gate pad, the data pad and the common pad further includes:

a lower pad electrode formed of the lowermost layer of the first conductive layer group;

an upper pad electrode formed of the upper layer of the first conductive layer group on the lower electrode; and

a contact hole passing through the gate insulating film to expose the lower pad electrode.

7. The device as claimed in claim 6, wherein the upper pad electrode is not overlapped with the contact hole to be protected by the gate insulating film.

8. The device as claimed in claim 1, further comprising a data link formed of the first conductive layer group to be connected, via a contact hole passing through the gate insulating film, to the data line.

9. The device as claimed in claim 8, further comprising:

a gate pad connected to the gate line;

a data pad connected to the data link; and

a common pad connected to the common line,

wherein each of the gate pad, the data pad and the common pad includes;

a lower pad electrode formed of the first conductive layer group;

a contact hole passing through the gate insulating film to expose the lower pad electrode; and

an upper pad electrode formed of the lowermost layer of the second conductive layer group to be connected, via the contact hole, to the lower pad electrode.

10. The device as claimed in claim 9, wherein the upper pad electrode of the data pad is electrically connected to the lowermost layer of the data line.

11. The device as claimed in claim 8, wherein the contact hole is positioned at an area to be sealed by a sealant upon joint of another substrate.

12. The device as claimed in claim 8, further comprising an alignment film on the data line, the source electrode, the drain electrode, the pixel electrode and the contact hole.

13. The device as claimed in claim 1, wherein the data line, the source electrode, the drain electrode and the pixel electrode are positioned at an area to be sealed by a sealant upon joint of another substrate.

14. The device as claimed in claim 1, further comprising an alignment film on the data line, the source electrode, the drain electrode and the pixel electrode.

15. The device as claimed in claim 1, wherein the semiconductor pattern is formed at a position to be provided with the thin film transistor.

16. The device as claimed in claim 1, wherein each of the first and second conductive layer groups has a structure having the upper conductive layer made of a copper metal layer or a copper alloy layer.

17. The device as claimed in claim 1, wherein at least one of the first and second conductive groups has step coverage having a stepwise shape.

18. The device as claimed in claim 1, wherein at least two layers of the semiconductor pattern, the source electrode, the drain electrode and the pixel electrode have step coverage having a substantially rectangular stepwise shape.