pFET nonvolatile memory

• US 8,111,558 B2
• Filed: 10/02/2007
• Issued: 02/07/2012
• Est. Priority Date: 05/05/2004
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Pesavento, Alberto, Hyde, John D.
• Primary Examiner(s): NGUYEN, DANG T
• Application Number:
  US11/865,777
• Publication Number:
  US 20080175050A1
• Time in Patent Office: 1,589 Days
• Field of Search: 365/185.28, 365/185.21, 365/185.18, 365/207, 365/189.09, 365/189.07, 365/185.26, 365/104, 365/149, 365/185.24
• US Class Current: 365/185.28
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
• CPC Class Codes: G11C 16/3486 Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: G11C 2216/26 Floating gate memory which is adapted to be one-time programmable [OTP], e.g. containing multiple OTP blocks permitting limited update ability

Abstract

A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.

Claims

1. A nonvolatile memory cell in an array of memory cells, comprising:

a first transistor having a floating gate coupled to a gate terminal, a source terminal coupled to receive a read enable signal and a drain terminal;

a first control capacitor structure having a first terminal coupled to a first data signal line and a second terminal coupled to said first floating gate;

a first tunneling capacitor structure having a first terminal coupled to a tunneling control signal line and a second terminal coupled to said first floating gate; and

a first readout switch having a first terminal coupled to said drain terminal of the first transistor and a second terminal coupled to a first readout node, a control node of said first readout switch coupled to a row select signal line, the first readout switch having first current at said first terminal substantially equal to drain current of the first transistor in a mode for performing a write operation on another nonvolatile memory cell in a same column of the array of the memory cells.

2. The nonvolatile memory cell of claim 1, further comprising:

a second transistor having a second floating gate coupled to a gate terminal, a source terminal and a drain terminal;

a second control capacitor structure having a first terminal coupled to a second data signal line and a second terminal coupled to said second floating gate;

a second tunneling capacitor structure having a first terminal coupled to the tunneling control signal line and a second terminal coupled to said second floating gate; and

a second readout switch having a first terminal coupled to said drain terminal of the second transistor and a second terminal coupled to a second readout node, a control node of said second readout switch coupled to the row select signal line, the second readout switch having second current at said first terminal equal to a drain current of the second transistor in the mode.

3. The nonvolatile memory cell of claim 1, wherein the first transistor is a P-channel Field Effect Transistor (pFET).

4. The nonvolatile memory cell of claim 1, wherein the nonvolatile memory cell does not include a second transistor having a drain terminal connected to said first terminal of the first readout switch.

5. The nonvolatile memory cell of claim 1, wherein the first transistor comprises a well terminal, the memory cell further comprising:

a read enable signal line coupled to the source terminal of the first transistor; and

a well control signal line coupled to the well terminal of the first transistor.

6. The nonvolatile memory cell of claim 5, wherein the well control signal line is biased to a first voltage and the read enable signal line is biased to a second voltage.

7. A method for programming memory cells in an array of differential transistor nonvolatile memory cells arranged in rows and columns of cells, the method comprising:

providing row control signals to the cells of a row of the array, the row control signals including tunneling control signals, row enable signals and row select signals;

providing column control signals to the cells of a column of the array, the column control signals including a first and a second data signal for each cell;

applying a first gate voltage to a first floating gate of a first transistor via a first tunneling capacitor structure and a first control capacitor structure, the first tunneling capacitor coupled between a tunneling control signal line and the first floating gate, the first control capacitor structure coupled between a first data signal line and the first floating gate;

applying a second gate voltage to a second floating gate of a second transistor via a second tunneling capacitor structure and the second control capacitor structure, the second tunneling capacitor coupled between the tunneling control signal line and the second floating gate, the second control capacitor structure coupled between a second data signal line and the second floating gate;

generating a first readout current at a first terminal of a first readout switch responsive to receiving a row select signal, said first terminal of the first readout switch coupled to a drain terminal of the first transistor, said first readout switch having a second terminal coupled to a first readout node and a control node of said readout switch for receiving a row select signal, wherein the first readout current at said first terminal of the first readout switch is substantially equal to drain current of the first transistor in a mode for performing a write operation on another nonvolatile memory cell in a same column of the array; and

generating a second readout current at a first terminal of a second readout switch responsive to receiving the row select signal, said first terminal of the second readout switch coupled to a drain terminal of the second transistor, said second readout switch having a second terminal coupled to a second readout node and a control node of said readout switch for receiving a row select signal, wherein the second readout current at said first terminal of the second readout switch is substantially equal to drain current of the second transistor in the mode.

8. The method of claim 7, in which

the tunneling control signals are voltage signals sufficient to cause Fowler-Nordheim tunneling across a dielectric insulating the first and second floating gates.

9. The method of claim 7, wherein the first and second transistors are P-channel Field Effect Transistors (pFETs).

10. The method of claim 7, wherein each of the first and second transistors comprises a well terminal, each differential nonvolatile transistor memory cell in the array further comprising:

a read enable signal line coupled to the source terminals of the first and second transistors; and

a well control signal line coupled to the well terminals of the first and second transistors.

11. The method of claim 10, wherein the well control signal line is biased to a first voltage and the read enable signal line is biased to a second voltage.

12. The method of claim 7, wherein the differential transistor nonvolatile memory cells do not include a third and fourth transistors having common gates coupled to a high voltage source and drain terminals connected to said first terminal of the first readout switch or said first terminal of the second readout switch.

13. An apparatus for programming memory cells in an array of differential transistor nonvolatile memory cells arranged in rows and columns of cells, the apparatus comprising:

means for providing row control signals to the cells of a row of the array, the row control signals including tunneling control signals, row enable signals and row select signals;

means for providing column control signals to the cells of a column of the array, the column control signals including a first and a second data signal for each cell;

means for applying a first gate voltage to a first floating gate of a first transistor via a first tunneling capacitor structure and a first control capacitor structure, the first tunneling capacitor coupled between a tunneling control signal line and the first floating gate, the first control capacitor structure coupled between a first data signal line and the first floating gate;

means for applying a second gate voltage to a second floating gate of a second transistor via a second tunneling capacitor structure and the second control capacitor structure, the second tunneling capacitor coupled between the tunneling control signal line and the second floating gate, the second control capacitor structure coupled between a second data signal line and the second floating gate;

means for controlling current from a drain of the first transistor to a first read out node responsive to receiving a row select signal, the means for controlling current having first current at a first terminal substantially equal to drain current of the first transistor in a mode for performing a write operation on another nonvolatile memory cell in a same column of the array; and

means for controlling current from a drain of the second transistor to a second read out node responsive to receiving a row select signal, the means for controlling current having second current at a second terminal substantially equal to drain current of the second transistor in the mode.

14. The apparatus of claim 13, in which

said tunneling control signals are voltage signals sufficient to cause Fowler-Nordheim tunneling across a dielectric insulating the first and second floating gates.

15. The apparatus of claim 13, wherein the first and second transistors are P-channel Field Effect Transistor (pFETs).

16. The apparatus of claim 13, wherein the first and second transistors each comprise a well terminal and a source terminal, each differential transistor memory cell in the array further comprising:

a read enable signal line coupled to the source terminals of the first and second transistors; and

a well control signal line coupled to the well terminals of the first and second transistors.

17. The apparatus of claim 16, wherein the well control signal line is biased to a first voltage and the read enable signal line is biased to a second voltage.

18. The apparatus of claim 13, wherein the differential transistor nonvolatile memory cells do not include third and forth transistors having a common gate coupled to a high voltage source and drain terminals connected to said first terminal or said second terminal.