Optimal channel design for memory devices for providing a high-speed memory interface

• US 8,111,566 B1
• Filed: 11/16/2007
• Issued: 02/07/2012
• Est. Priority Date: 11/16/2007
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Ferolito, Philip Arnold, Rajan, Suresh Natarajan, Smith, Michael John Sebastian, Wang, Min
• Primary Examiner(s): Tran, Andrew Q
• Application Number:
  US11/941,589
• Time in Patent Office: 1,544 Days
• Field of Search: 365/72, 365/63, 365/51, 365/198, 365/191
• US Class Current: 365/198
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4234 being a memory bus

Abstract

A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology.

Claims

1. A system, comprising:

a plurality of memory devices; and

at least one channel configured to provide an electrical communication between a memory controller and a first memory device of the plurality of memory devices, the channel comprising;

a micro-via;

a circuit configured to provide impedance matching between the memory controller and the first memory device, the circuit including a first resistor;

a second resistor configured to couple with the memory controller; and

a transmission line having a first end and a second end, the first end of the transmission line coupled with the first resistor and the second end of the transmission line coupled with the second resistor.

2. The system of claim 1, wherein the channel is a data read/write channel.

3. The system of claim 2, wherein the first resistor has a resistance of 20 ohms.

4. The system of claim 2, wherein the second resistor has a resistance between 8 ohms and 12 ohms.

5. The system of claim 2, wherein the transmission line has an impedance between 35 ohms and 45 ohms.

6. The system of claim 1, wherein the channel is a command/address channel.

7. The system of claim 6, wherein the first resistor has a resistance of 100 ohms.

8. The system of claim 6, wherein the second resistor has a resistance between 20 ohms and 24 ohms.

9. The system of claim 6, wherein the transmission line has an impedance between 81 ohms and 99 ohms.