System comprising a state-monitoring memory element
First Claim
1. A system, comprising:
- at least one state-monitoring memory element having a reduced ability to retain a logic state compared to a normal memory element, the at least one state-monitoring memory element configured to lose the logic state before the normal memory element when a degraded input supply voltage drops below a threshold voltage;
a circuit element, distinct from the at least one state-monitoring memory element, configured to cause the at least one state-monitoring memory element but not the normal memory element to have the reduced ability; and
a failure detection element configured to detect a failure by the at least one state-monitoring memory element to retain the logic state and responsive to the detection to generate an indicator of the failure, and wherein the failure detection element is further configured to issue an interrupt signal to a system processor.
5 Assignments
0 Petitions
Accused Products
Abstract
Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC'"'"'s state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be distributed in different locations on the IC for better coverage.
-
Citations
16 Claims
-
1. A system, comprising:
-
at least one state-monitoring memory element having a reduced ability to retain a logic state compared to a normal memory element, the at least one state-monitoring memory element configured to lose the logic state before the normal memory element when a degraded input supply voltage drops below a threshold voltage; a circuit element, distinct from the at least one state-monitoring memory element, configured to cause the at least one state-monitoring memory element but not the normal memory element to have the reduced ability; and a failure detection element configured to detect a failure by the at least one state-monitoring memory element to retain the logic state and responsive to the detection to generate an indicator of the failure, and wherein the failure detection element is further configured to issue an interrupt signal to a system processor. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A method, comprising:
-
configuring a state-monitoring memory element to have a reduced ability to retain a logic state compared to a normal memory element, by using a circuit element that is distinct from the state-monitoring memory element to cause the reduced ability detecting a failure by the state-monitoring memory element to retain an initial logic state responsive to an input supply voltage coupled to the state-monitoring memory element dropping below a threshold voltage; generating an indicator of failure responsive to detecting the failure by the state-monitoring memory element earlier than a failure of the normal memory element; and generating an interrupt signal in response to detecting the failure in the state-monitoring memory element. - View Dependent Claims (7, 8, 9, 10, 11)
-
-
12. A system, comprising:
-
means for configuring a state-monitoring memory element to have a reduced ability to retain a logic state compared to a normal memory element, such that the state-monitoring memory element is more likely to experience logic state loss before the normal memory element when an input supply voltage associated with the state-monitoring memory element drops below a threshold voltage; and a failure detection element configured to detect a failure by the state-monitoring memory element to retain the logic state by comparing an initial logic state of the state-monitoring memory element with a current logic state of the state-monitoring memory element, and further configured to generate an indicator of failure responsive to detecting the failure by the state-monitoring memory element. - View Dependent Claims (13, 14, 15, 16)
-
Specification