Device and method for fast transition from preamble synchronization to data demodulation in direct sequence spread spectrum (DSSS) communications

• US 8,111,734 B2
• Filed: 01/14/2008
• Issued: 02/07/2012
• Est. Priority Date: 01/14/2008
• Status: Active Grant

• Current Assignee: The Boeing Co.
• Original Assignee: The Boeing Co.
• Inventors: Wang, Xinyu, Gahler, Marcus, Higgins, Robert P., Norris, Paul R.
• Primary Examiner(s): Payne, David C.
• Assistant Examiner(s): HEARD, ERIN FILE
• Application Number:
  US12/013,542
• Publication Number:
  US 20090180524A1
• Time in Patent Office: 1,485 Days
• Field of Search: 375/147
• US Class Current: 375/147
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 1/7085 using a code tracking loop, e.g. a delay-locked loop
• CPC Class Codes: H04B 1/7093 Matched filter type

Abstract

A device for fast transition from preamble synchronization of a received baseband signal to demodulation of the received baseband signal may include a baseband chip tracking loop to generate an offset tracking value to track any initial chip phase offset and Doppler-caused baseband chip frequency drift associated with the received baseband signal. The device may also include a numerical controlled oscillator to correct any Doppler-caused phase rotation associated with the received signal. The device may additionally include a preamble synchronization unit to detect a preamble of the received baseband signal, and to measure a chip phase offset and a baseband Doppler frequency shift associated with the received baseband signal. The chip phase offset may be used to set an initial chip phase offset value of the chip tracking loop so that the chip tracking loop starts with approximately a zero pull-in error. The baseband Doppler frequency shift may be used to set initial frequency offset values in the chip tracking loop and the numerical controlled oscillator so that both start with substantially near-zero offset errors for substantially immediate demodulation of the received signal. The device may further include an output device to output the data demodulated from the received baseband signal.

Claims

1. A device for fast transition from preamble synchronization of a received signal to demodulation of the received signal, comprising:

a chip tracking loop to generate an offset tracking value to track any initial chip phase offset and Doppler-caused chip frequency drift associated with the received signal;

a numerical controlled oscillator to correct any Doppler-caused phase rotation associated with the received signal;

a preamble synchronization unit to detect a preamble of the received signal, and to measure a chip phase offset and a Doppler frequency shift associated with the received signal, wherein the chip phase offset is used to set an initial chip phase offset value of the chip tracking loop so that the chip tracking loop starts with approximately a zero pull-in error, and the Doppler frequency shift is used to set initial frequency offset values in the chip tracking loop and the numerical controlled oscillator so that both start with near-zero offset errors for demodulation of the received signal; and

an output device to output the data demodulated from the received signal.

2. The device of claim 1, further comprising a pseudo-random noise generator to generate pseudo-random noise chip sequences to reconstruct data from the received signal, wherein the pseudorandom noise chip sequences correspond to those sequences used for data spreading in a transmitter that transmitted the received signal.

3. The device of claim 2, further comprising a variable-delay poly-phase pulse matched filter unit to select a filter from a variable-delay poly-phase filter bank to shape a waveform of the received signal and to correct the chip phase offset between the received signal waveform and the chip sequences generated by the pseudo-random noise generator.

4. The device of claim 1, further comprising a data demodulation unit to demodulate the received signal to extract a payload data portion of the received signal.

5. The device of claim 4, further comprising a data encoder unit to encode the demodulated payload data to wipe out any data modulation impact on a chip tracking process in the chip tracking loop.

6. The device of claim 1, further comprising a chip phase offset estimation unit to measure an initial chip phase offset between the received signal and a chip sequence generated by a pseudo-random noise generator to reconstruct data from the received signal.

7. The device of claim 6, wherein the chip phase offset estimation unit comprises:

a set of interpolation filters to derive interpolated signal amplitudes at various pre-determined chip phase offset positions; and

a comparator to select a maximal interpolated amplitude and corresponding chip phase offset.

8. The device of claim 7, further comprising a post-processing unit to adjust for an early detection of a preamble synchronization peak position.

9. The device of claim 1, further comprising means for correcting an initial chip phase offset and the Doppler frequency shift to eliminate any initial pull-in time in the chip tracking loop and to start data demodulation at an optimal chip energy to noise ratio after synchronization of the preamble of the received signal.

10. The device of claim 9, further comprising a timing and control logic unit to determine step-by-step operations to apply the initial chip phase offset and Doppler frequency shift to loop filters in the chip tracking loop and numerical controlled oscillator.

11. The device of claim 1, wherein the preamble synchronization unit comprises:

an inner code matched filter for coherent accumulation of signal energy from chips within one inner code sequence, wherein the inner code matched filter receives an output from the numerical controlled oscillator;

a differential binary phase shift keying unit to apply a differential phase shift keying demodulation to remove any Doppler-caused phase rotation across the outer code sequence symbols;

an outer code matched filter for non-coherent accumulation of signal energy from an entire outer code sequence;

a cordic arctan unit to calculate an amplitude and phase of each accumulated sample from the outer code matched filter;

a Doppler frequency converter unit to convert a phase value from the cordic arctan unit into a Doppler frequency; and

a chip phase offset estimation unit to determine a maximal amplitude of an interpolated sample and its corresponding subchip-interval offset value from the cordic arctan unit.

12. The device of claim 1, further comprising a unit to despread the received signal that is spread modulated at a transmitter with an offset quadrature phase shift keying method.

13. The device of claim 12, wherein the unit to despread the received signal using offset quadrature phase shift keying comprises:

a module to generate an output in-phase signal using signal processing defined by (XId·

Pi+XQ·

PQ)+(Xi−

1³1+XQd·

PQ); and

a module to generate a quadrature signal using signal processing defined by (−

Xid·

PQ+XQ·

PI)−

(Xi·

PQ−

XQd·

Pi), wherein XI is an in-phase component of an input signal;

XQ is the quadrature component of the input signal;

)(id is an in-phase component of the input signal with one sample delay;

XQd is the quadrature component of the input signal with one sample delay;

PI and PQ are in-phase and quadrature components of a PN sequence used for OQPSK spreading.

14. A communications device, comprising:

a receiver to receive a communications signal;

a preamble synchronization stage to detect a preamble of the received communications signal;

a data demodulation stage to demodulate the received communications signal; and

a burst modem architecture for transition from the preamble synchronization stage to the data demodulation stage in Direct Sequence Spread Spectrum (DSSS) communication with a significant Doppler frequency shift, wherein the preamble synchronization stage measures a chip phase offset and a Doppler frequency shift associated with the received communications signal, wherein the chip phase offset is used to set an initial chip phase offset value of a chip tracking loop so that the chip tracking loop starts with approximately a zero pull-in error, and the Doppler frequency shift is used to set initial frequency offset values in the chip tracking loop and a numerical controlled oscillator so that both start with near-zero offset errors for demodulation of the received communications signal; and

an output device to output the demodulated data.

15. The communications device of claim 14, further comprising:

a preamble synchronization unit to detect the preamble of the received signal, and to measure a chip phase offset and a Doppler frequency shift associated with the received signal.

16. The communications device of claim 14, further comprising:

a pseudo-random noise (PN) generator to generate copies of PN chip sequences identical to those in a transmitter for data spreading;

a variable-delay poly-phase pulse matched filter unit to receive the signal and to select a filter from a variable-delay poly-phase filter bank to shape a waveform of the received signal and to correct a chip phase offset between the received signal waveform and the chip sequences generated by the pseudo-random noise generator;

wherein the numerical controlled oscillator corrects any Doppler-caused phase rotation associated with the received signal;

a preamble synchronization unit to detect arrival of the communications signal, to estimate a Doppler shift in the communications signal and to estimate an initial chip phase offset between the communications signal and the chip sequence generated by the PN generator;

wherein the chip tracking loop continuously tracks a chip phase offset between the received signal waveform and the chip sequences generated by the PN generator;

a data demodulation unit to demodulate the received signal to extract a payload data portion of the received signal; and

a data encoder unit to encode the demodulated payload data to wipe out any data modulation impact on a chip tracking process in the chip tracking loop.

17. A method for fast transition from preamble synchronization of a received signal to demodulation of the received signal, comprising:

detecting a preamble of the received signal;

measuring a chip phase offset and a Doppler frequency shift associated with the received signal;

setting an initial chip phase offset value of a chip tracking loop in response to the measured chip phase offset so that the chip tracking loop starts with approximately a zero pull-in error;

setting initial frequency offset values in the chip tracking loop and a numerical controlled oscillator in response to the measured Doppler frequency shift so that the chip tracking loop and the numerical controlled oscillator start with near-zero offset errors for demodulation of the received signal;

demodulating the received signal to extract payload data; and

outputting the payload data.

18. The method of claim 17, further comprising:

generating an offset tracking value to track any Doppler-caused chip frequency drift associated with the received signal; and

correcting any Doppler-caused phase rotation associated with the received signal.

19. The method of claim 17, further comprising selecting a filter from a variable-delay poly-phase filter bank to shape a waveform of the received signal and to correct the chip phase offset between the received signal waveform and chip sequences generated by a pseudo-random noise generator.

20. The method of claim 17, further comprising encoding the demodulated payload data to wipe out any data modulation impact on a chip tracking process in the chip tracking loop.

21. The method of claim 17, further comprising correcting the initial chip phase offset and the Doppler frequency shift to eliminate any initial pull-in time in the chip tracking loop and to start data demodulation at an optimal chip energy to noise ratio after synchronization of the preamble of the received signal.

22. The method of claim 17, further comprising:

accumulating signal energy from chips within one inner code sequence,

applying a differential phase shift keying modulation to remove any Doppler-caused phase rotation across outer code sequence symbols;

accumulating signal energy from an entire outer code sequence;

calculating an amplitude and phase of each accumulated sample from an outer code matched filter;

converting a phase value from a cordic arctan unit into a Doppler frequency; and

determining a maximal amplitude of an interpolated sample and its corresponding sub-chip-interval offset value from the cordic arctan unit.

23. The method of claim 17, further comprising despreading the received signal using offset quadrature phase shift keying.

24. The method of claim 23, further comprising:

generating an output in-phase signal using signal processing defined by (Xid·

Pi+X_Q·

P_Q)+(Xi·

PI+X_Qd·

P_Q); and

generating a quadrature signal using signal processing defined by (−

Xid·

P_Q+X_Q·

PI)−

(XI−

PQ−

XQd·

PI), wherein XI is an in-phase component of an input signal;

XQ is the quadrature component of the input signal;

)(Id is an in-phase component of the input signal with one sample delay;

Xcld is the quadrature component of the input signal with one sample delay;

PI and PQ are in-phase and quadrature components of a PN sequence used for OQPSK spreading.