Apparatus and method for separating a circuit pattern into multiple circuit patterns
First Claim
1. A method for separating an original circuit pattern to be printed on a wafer via a lithography process, into multiple circuit patterns, comprising the steps of:
- obtaining circuit pattern data;
identifying a model of the lithography process;
performing a simulation of the lithography process using the model to obtain image quality information on edges of polygons in the circuit pattern based on the circuit pattern data;
identifying edges that are expected to be printed properly and edges that are expected to be printed improperly on the wafer according to the image quality information obtained from the simulation; and
separating the original circuit pattern into multiple circuit patterns such that each of the multiple patterns does not have any improperly printed edges.
2 Assignments
0 Petitions
Accused Products
Abstract
A method for separating an original circuit pattern to be printed on a wafer, into multiple circuit patterns is disclosed. Simulation to obtain an image log-slope (ILS), normalized image log-slope (NILS), or any other characteristic of an image quality on edges of polygons in the circuit pattern obtained from circuit pattern data is performed. Properly printed edges and not-properly printed edges are identified according to a criterion of an ILS level. The original circuit pattern is separated into multiple circuit patterns such that each of the multiple patterns does not have any not-properly printed edges.
20 Citations
22 Claims
-
1. A method for separating an original circuit pattern to be printed on a wafer via a lithography process, into multiple circuit patterns, comprising the steps of:
-
obtaining circuit pattern data; identifying a model of the lithography process; performing a simulation of the lithography process using the model to obtain image quality information on edges of polygons in the circuit pattern based on the circuit pattern data; identifying edges that are expected to be printed properly and edges that are expected to be printed improperly on the wafer according to the image quality information obtained from the simulation; and separating the original circuit pattern into multiple circuit patterns such that each of the multiple patterns does not have any improperly printed edges. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. An apparatus for separating, using a computer processor, an original circuit pattern to be printed on a wafer via a lithography process, into multiple circuit patterns, comprising:
-
a first unit in the computer processor configured for performing a simulation of the lithography process using a model of the lithography process to obtain image quality information on edges of polygons in the circuit pattern obtained from circuit pattern data; a second unit in the computer processor configured for identifying edges that are expected to be printed properly and edges that are expected to be printed improperly on the wafer according to the image quality information obtained from the simulation; and a third unit in the computer processor configured for separating the original circuit pattern into multiple circuit patterns such that each of the multiple patterns does not have any improperly printed edges. - View Dependent Claims (9, 10, 11, 12, 13, 14)
-
-
15. A non-transitory computer readable storage medium storing a computer program for separating an original circuit pattern to be printed on a wafer via a lithography process, into multiple circuit patterns, when executed, causing a computer to perform the steps of:
-
obtaining circuit pattern data; identifying a model of the lithography process; performing simulation of the lithography process using the model to obtain image quality information on edges of polygons in the circuit pattern based on the circuit pattern data; identifying edges that are expected to be printed properly and edges that are expected to be printed improperly on the wafer according to the image quality information obtained from the simulation; and separating the original circuit pattern into multiple circuit patterns such that each of the multiple patterns does not have any improperly printed edges. - View Dependent Claims (16, 17, 18, 19, 20, 21)
-
-
22. A device manufacturing method using a lithography process comprising the steps of:
-
(a) providing a substrate that is at least partially covered by a layer of radiation-sensitive material; (b) providing a projection beam of radiation using an imaging system; (c) using patterns on masks to endow the projection beam with patterns in its cross-section; (d) projecting the patterned beam of radiation onto a target portion of the layer of radiation-sensitive material, wherein in step (c), providing a pattern on a mask includes the steps of; performing a simulation of the lithography process using a model of the lithography process to obtain image quality information on edges of polygons in a circuit pattern obtained from circuit pattern data; identifying edges that are expected to be printed properly and printed edges that are expected to be printed improperly on the wafer according to the image quality information obtained from the simulation; and separating the original circuit pattern into multiple circuit patterns to be assigned to the masks, respectively, such that each of the multiple patterns does not have any improperly printed edges.
-
Specification