System and methods for parametric test time reduction

• US 8,112,249 B2
• Filed: 12/22/2008
• Issued: 02/07/2012
• Est. Priority Date: 12/22/2008
• Status: Active Grant

• Current Assignee: Optimal Plus Ltd. (Emerson Electric Company)
• Original Assignee: Optimaltest, Ltd. (Emerson Electric Company)
• Inventors: Gurov, Leonid, Chufarovsky, Alexander, Balog, Gil
• Primary Examiner(s): Dunn, Drew A
• Assistant Examiner(s): SUN, XIUQIN
• Application Number:
  US12/341,431
• Publication Number:
  US 20100161276A1
• Time in Patent Office: 1,142 Days
• Field of Search: 702/181, 702/82, 703/7, 345/440, 250/282, 714/736, 382/141
• US Class Current: 702/181
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A parametric test time reduction method for reducing time expended to conduct a test program flow on a population of semiconductor devices, the test program flow comprising at least one parametric test having a specification defining a known pass value range characterized in that a result of the test is considered a passing result if the result falls within the known pass value range, the method including: computing an estimated maximum test range, at a given confidence level, on a validation set including a subset of the population of semiconductor devices, the estimated maximum test range including the range of values into which all results from performing the test on the set will statistically fall at the given confidence level and at least partly disabling the at least one parametric test based at least partly on a comparison of the estimated maximum test range and the known pass value range.

Claims

1. A parametric test time reduction method for reducing time expended to conduct a test program flow on a population of semiconductor devices, the test program flow comprising at least one parametric test having a specification which defines a known pass value range wherein a result of the test is considered a passing result if the result falls within said known pass value range, the method comprising:

for at least one parametric test, computing an estimated maximum test range, at a given confidence level, on a validation set comprising a subset of the population of semiconductor devices, the estimated maximum test range comprising the range of values into which all results from performing said test on said set will statistically fall at said given confidence level, said validation set defining a complementary set including all semiconductors included in said population and not included in said validation set; and

at least partly disabling said at least one parametric test based at least partly on a comparison of said estimated maximum test range and said known pass value range,

wherein said computing an estimated maximum test range comprises;

performing said parametric test on semiconductor devices included in said validation set, thereby to generate results for said semiconductor devices respectively and selecting from among said semiconductor devices at least one extreme subset including at least one of a high-scoring subset including all devices whose results exceed a high cut-off point and a low-scoring subset including all devices whose results fall below a low cut-off point;

plotting results of said at least one extreme subset as a normal quantile probability plot having a zero probability axis and fitting a plurality of curves to a plurality of subsets of said results respectively;

extending each of said plurality of curves to said zero probability axis thereby to define a corresponding plurality of intersection points and thereby to define a zero probability range along said zero probability axis within which all said intersection points fall; and

defining said estimated maximum test range to include said zero probability range.

2. A method according to claim 1 wherein said test is at least partly disabled if said estimated maximum test range falls at least partly within said known pass value range.

3. A method according to claim 1 wherein said test is at least partly disabled if said estimated maximum test range falls entirely within said known pass value range.

4. A method according to claim 1 and also comprising making an on-the-fly determination as to whether said estimated maximum test range falls at least partly within said known pass value range and using said on-the-fly determination as a condition for at least partly re-enabling said at least one parametric test, said on-the-fly determination comprising re-computing said estimated maximum test range on an on-the-fly generated validation set comprising at least one tested semiconductor device absent from said validation set.

5. A method according to claim 4 and also comprising at least partly re-enabling said at least one parametric test, irrespective of said on-the-fly determination, if even one semiconductor device within said on-the-fly generated validation set fails said parametric test.

6. A method according to claim 1 and also comprising at least partly disabling said at least one parametric test, irrespective of said comparison, if even one semiconductor device within said validation set fails said parametric test.

7. A method according to claim 1 wherein said estimated maximum test range includes said zero probability range extended outward by a safety factor.

8. A method according to claim 1 wherein said subsets of said results comprise result pairs.

9. A method according to claim 1 wherein said plurality of subsets of said results comprises all result pairs which are adjacent.

10. A method according to claim 1 wherein said plurality of subsets of said results comprises only result pairs which are adjacent.

11. A method according to claim 1 wherein said known pass value range has only a single endpoint and wherein said at least one extreme subset comprises only one extreme subset.

12. A method according to claim 1 wherein said known pass value range has two endpoints.

13. A method according to claim 1 wherein said population of semiconductor devices is mounted on wafers and said test program flow comprises a wafer sort test program flow.

14. A method according to claim 1 wherein said population of semiconductor devices comprises a population of packaged units said test program flow comprises an FT (final test) test program flow.

15. A method according to claim 1 wherein said test is at least partly disabled if said estimated maximum test range falls at least partly within said known pass value range.

16. A method according to claim 1 wherein said test is at least partly disabled if said estimated maximum test range falls entirely within said known pass value range.

17. A method according to claim 1 and also comprising making an on-the-fly determination as to whether said estimated maximum test range falls entirely within said known pass value range and using said on-the-fly determination as a condition for at least partly re-enabling said at least one parametric test, said on-the-fly determination comprising re-computing said estimated maximum test range on an on-the-fly generated validation set comprising at least one tested semiconductor device absent from said validation set.

18. A method according to claim 17 wherein said condition comprises a necessary condition.

19. A method according to claim 17 wherein said condition comprises a sufficient condition.

20. A method according to claim 1 wherein said at least one parametric test is conducted at a plurality of sites in parallel and wherein the estimated maximum test range is computed separately for each site from among said plurality of sites whose test results statistically differ from test results of other sites in said plurality of sites.

21. A method according to claim 1 where said computing comprises:

normalizing test results of said subset of the population of semiconductor devices, thereby to generate normalized test results; and

computing said estimated test range based on said normalized test results.

22. A non-transitory computer-readable medium having a computer readable program code embodied therein, the computer readable program code being adapted to be executed to implement the method of claim 1.