Apparatus for simulating an aspect of a memory circuit

• US 8,112,266 B2
• Filed: 10/30/2007
• Issued: 02/07/2012
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Schakel, Keith R., Smith, Michael John Sebastian, Wang, David T., Weber, Frederick Daniel
• Primary Examiner(s): Proctor, Jason
• Assistant Examiner(s): Kim, Eunhee
• Application Number:
  US11/929,500
• Publication Number:
  US 20080133825A1
• Time in Patent Office: 1,561 Days
• Field of Search: 703/24
• US Class Current: 703/24
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Such aspect includes a signal, a capacity, a timing, and/or a logical interface.

Claims

1. An apparatus comprising:

an interface circuit operable to;

receive, from a system, (1) write data to be stored on at least one physical memory device of a plurality of physical memory devices, and (2) a first refresh control signal;

communicate the write data, after a first delay, to the at least one physical memory device; and

in response to receiving the first refresh control signal, communicate within a first time span a distinct second refresh control signal to each of a first subset of the plurality of physical memory devices and a second subset of the plurality of physical memory devices, wherein the interface circuit includes;

first storage to store emulated memory attributes associated with one or more emulated memory devices; and

second storage to store physical memory attributes associated with at least one of the one or more physical memory devices,

where the interface circuit is operable to emulate one or more memory devices based on the emulated memory attributes,

where the emulated memory attributes include a first latency and the physical memory attributes include a second latency, the first latency being greater than the second latency,

where the first latency includes at least one of a first row address strobe to column address strobe latency (tRCD), a first row precharge latency (tRP), a first activate to precharge latency (tRAS), or a first row cycle time (tRC), and the second latency includes at least one of a second tRCD, a second tRP, a second tRAS, or a second tRC,

where the first delay is based on the first latency and the second latency, and

where the first time span is specified by a refresh latency (tRFC) associated with the one or more emulated memory devices.

2. The apparatus of claim 1, wherein the first delay is based on a difference between the first latency and the second latency.

3. The apparatus of claim 1, wherein the first delay is greater than or equal to one clock cycle.

4. The apparatus of claim 1, wherein at least two of the emulated memory attributes are different from corresponding physical memory attributes.

5. The apparatus of claim 1 wherein the interface circuit is further operable to:

receive read data from at least one of the one or more physical memory devices; and

communicate the read data, after a second delay, to the system, where the second delay is based on the first latency and the second latency.

6. The apparatus of claim 1 wherein the first storage and second storage include read or write capable memory.

7. The apparatus of claim 1 wherein the first storage and second storage include hard-wired logic.

8. The apparatus of claim 1 wherein the distinct second refresh control signal includes a copy of the first refresh control signal.

9. The apparatus of claim 1 wherein the interface circuit is further operable to communicate the distinct second refresh control signal to each of the first subset and the second subset at separate times to minimize power consumption of the plurality of physical memory devices.

10. The apparatus of claim 9 wherein the interface circuit is further operable to communicate the distinct second refresh control signal to each of the first subset and the second subset at separate times to minimize a current draw of the interface circuit and the plurality of physical memory devices.

11. An apparatus comprising:

a plurality of physical memory devices;

an interface circuit operable to;

receive, from a system, (1) write data to be stored on one or more of the plurality of physical memory devices and (2) a first refresh control signal;

communicate the write data, after a first delay, to the one or more physical memory devices; and

in response to receiving the first refresh control signal, communicate within a first time span a distinct second refresh control signal to each of a first subset of the plurality of physical memory devices and a second subset of the plurality of physical memory devices, wherein the interface circuit includes;

first storage to store emulated memory attributes associated with one or more emulated memory devices; and

second storage to store physical memory attributes associated with one or more of the plurality of physical memory devices,

where the interface circuit is operable to emulate one or more memory devices based on the emulated memory attributes,

where the emulated memory attributes include a first latency and the physical memory attributes include a second latency, the first latency being greater than the second latency,

where the first latency includes at least one of a first row address strobe to column address strobe latency (tRCD), a first row precharge latency (tRP), a first activate to precharge latency (tRAS), or a first row cycle time (tRC), and the second latency includes at least one of a second tRCD, a second tRP, a second tRAS, or a second tRC,

where the first delay is based on the first latency and the second latency; and

where the first time span is specified by a refresh latency (tRFC) associated with the one or more emulated memory devices.

12. The apparatus of claim 11, wherein the first delay is based on a difference between the first latency and the second latency.

13. The apparatus of claim 11, wherein the first delay is greater than or equal to one clock cycle.

14. The apparatus of claim 11 wherein the interface circuit is further operable to:

receive read data from at least one of the plurality of physical memory devices; and

communicate the read data, after a second delay, to the system, where the second delay is based on the first latency and the second latency.

15. The apparatus of claim 11 wherein the first storage and second storage include read or write capable memory.

16. The apparatus of claim 11 wherein the first storage and second storage include hard-wired logic.

17. The apparatus of claim 11 wherein the distinct second refresh control signal includes a copy of the first refresh control signal.

18. The apparatus of claim 11 wherein the interface circuit is further operable to communicate the distinct second refresh control signal to each of the first subset and the second subset at separate times to minimize power consumption of the plurality of physical memory devices.

19. The apparatus of claim 18 wherein the interface circuit is further operable to communicate the distinct second refresh control signal to each of the first subset and the second subset at separate times to minimize a current draw of the interface circuit and the plurality of physical memory devices.