Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC

• US 8,112,468 B1
• Filed: 05/25/2007
• Issued: 02/07/2012
• Est. Priority Date: 03/22/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Redgrave, Jason, Caldwell, Andrew, Teig, Steven
• Primary Examiner(s): Ngo, Chuong D
• Application Number:
  US11/754,262
• Time in Patent Office: 1,719 Days
• Field of Search: 708/625, 708/627, 708/632
• US Class Current: 708/625
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence

Abstract

Some embodiments provide a method of performing a mathematical operation on a set of operands. The mathematical operation includes several sub-operations. The method examines several bits of at least one operand at a time and depending on the value of these bits, reconfigures a single logic circuit to perform one of the sub-operations to generate a partial result of the mathematical operation. In some embodiments, the logic circuit is reconfigured by receiving a first set of configuration data that cause the logic circuit to reconfigure to perform a first sub-operation operation and a second set of configuration data that cause the logic circuit to reconfigure to perform a second sub-operation. In some embodiments, the logic circuit receives different inputs based on the value of the bits being examined. In some embodiments, the mathematical operation is multiplication and the sub-operations are addition and subtraction.

Claims

1. An electronic device comprising:

a memory device for storing configuration data; and

an integrated circuit (“

IC”

), the IC comprising;

a reconfigurable logic circuit;

a signal generator for generating first and second selection signals based on a value of a particular number of bits of a multiplier of a multiplication operation;

a set of configurable circuits for supplying a plurality of inputs to the reconfigurable logic circuit;

first and second sets of configuration storage cells for storing first and second configuration data sets, wherein the first configuration data set is for configuring the reconfigurable logic circuit to perform an addition operation and the second configuration data set is for configuring the reconfigurable logic circuit to perform a subtraction operation;

third, fourth and fifth sets of configuration storage cells for storing third, fourth and fifth configuration data sets, wherein the third, fourth and fifth configuration data sets are for configuring the set of configurable circuits to supply to the reconfigurable logic circuit either a value of a multiplicand, twice the value of the multiplicand, or a value of 0;

a first selection circuit for supplying one of the first and second configuration data sets to the reconfigurable logic circuit based on the first selection signal, wherein, based on the configuration data set supplied to the reconfigurable logic circuit, the reconfigurable logic circuit performs either the addition operation or the subtraction operation in order to generate a partial result of the multiplication operation; and

a second selection circuit for selecting, based on the second selection signal, one of the third, fourth and fifth configuration data sets for the set of configurable circuits.

2. The electronic device of claim 1, wherein said particular number of bits is three.

3. A method of performing a multiplication operation between a multiplier and a multiplicand, the multiplication operation comprising at least one of an addition operation and a subtraction operation performed by a particular logic circuit, the method comprising:

examining a plurality of bits of the multiplier;

based on the examination of the plurality of bits of the multiplier, (i) generating a first selection signal for selecting one of first and second configuration data sets stored in first and second sets of configuration storage cells, wherein the first configuration data set is for configuring the particular logic circuit to perform the addition operation and the second configuration data set is for configuring the particular logic circuit to perform the subtraction operation, (ii) generating a second selection signal for selecting one of third, fourth and fifth configuration data sets stored in third, fourth and fifth sets of configuration storage cells, wherein each of the third, fourth and fifth configuration data sets is for selecting one of a plurality of inputs to provide to the particular logic circuit;

based on the generated first selection signal, supplying one of the first and second configuration data sets from one of the corresponding first and second sets of configuration storage cells to the particular logic circuit;

based on the generated second selection signal, selecting one of the plurality of inputs to provide to the particular logic circuit; and

based on the configuration data set supplied to the particular logic circuit and the selected input provided to the particular logic circuit, performing either the addition operation or the subtraction operation to generate a partial result of the multiplication operation.

4. The method of claim 3, wherein examining the plurality of bits of the multiplier comprises examining three bits of the multiplier.

5. The method of claim 3, wherein the plurality of inputs comprises a value of 0, a value of the multiplicand, and two times the value of the multiplicand.

6. An integrated circuit (“

IC”

) for performing a multiplication operation comprising at least one of an addition operation and a subtraction operation, the IC comprising;

a reconfigurable logic circuit;

a signal generator for generating first and second selection signals based on a value of a particular number of bits of a multiplier of the multiplication operation;

a set of configurable circuits for supplying a plurality of inputs to the reconfigurable logic circuit;

first and second sets of configuration storage cells for storing first and second configuration data sets, wherein the first configuration data set is for configuring the reconfigurable logic circuit to perform the addition operation and the second configuration data set is for configuring the reconfigurable logic circuit to perform the subtraction operation;

third, fourth and fifth sets of configuration storage cells for storing third, fourth and fifth configuration data sets, wherein the third, fourth and fifth configuration data sets are for configuring the set of configurable circuits to supply as input to the reconfigurable logic circuit either a value of a multiplicand, twice the value of the multiplicand, or a value of 0;

a first selection circuit for supplying one of the first and second configuration data sets to the reconfigurable logic circuit based on the first selection signal, wherein, based on the configuration data set supplied to the reconfigurable logic circuit, the reconfigurable logic circuit performs either the addition operation or the subtraction operation in order to generate a partial result of the multiplication operation; and

a second selection circuit for selecting, based on the second selection signal, one of the third, fourth and fifth configuration data sets for the set of configurable circuits.

7. The IC of claim 6, wherein said particular number of bits is three.