Method and apparatus for detecting the type of interface to which a peripheral device is connected

• US 8,112,556 B2
• Filed: 05/31/2011
• Issued: 02/07/2012
• Est. Priority Date: 07/08/1998
• Status: Expired due to Fees

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Hanson, Mark T., Featherston, Lord Nigel, Sherman, Nathan C., Drake, Victor P., Mullins, Keith, Holo, David L.
• Primary Examiner(s): Hafiz, Tariq
• Assistant Examiner(s): Hassan, Aurangzeb
• Application Number:
  US13/118,927
• Publication Number:
  US 20110231585A1
• Time in Patent Office: 252 Days
• Field of Search: 710/1, 710/8, 710/15, 710/16, 710/104, 713/100
• US Class Current: 710/16
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination

Abstract

A peripheral device, with first and second communication conductors, is connectable to a computer having one of a first interface and a second interface. The first interface communicates with the peripheral device over a differential data connection having a first data conductor and a second data conductor. The second interface communicates with the peripheral device over a clock conductor and a single ended data connection which includes a data conductor. The peripheral device includes an interface detection component coupled to the first and second communication conductors to detect which of the first and second interfaces the peripheral device is connected to.

Claims

1. A peripheral device connectable to a computer having one of a first interface and a second interface, the first interface communicating with the peripheral device over a differential data connection including a first data conductor and a second data conductor connected to a first voltage potential with first and second resistive elements, respectively, and the second interface communicating with the peripheral device over a single ended data connection, including a first data conductor and a clock conductor pulled to a second voltage potential by third and fourth resistive elements, respectively, the peripheral device comprising:

first and second communication conductors configured for connection to the first and second data conductors in the differential data connection when the computer includes the first interface, and configured for connection to the first data conductor in the single ended data connection and the clock conductor when the computer includes the second interface;

an interface detection component, coupled to the first and second communication conductors, including connection elements selectable connecting the first and second communication conductors to a predetermined voltage potential and a signal detector configured to detect signal levels on the first and second communication conductors to detect which of the first and second interfaces the peripheral device is connected to when the connection elements are deselected to selectively disconnect the first and second communication conductors from the predetermined voltage potential and to provide a connection output indicative of the detected interface; and

a controller component, coupled to the interface detection component, configured to communicate between the peripheral device and the computer over the first and second communication conductors according to a protocol corresponding to the detected interface based on the connection output;

wherein the controller component comprises;

a first controller configured to control communication according to a first protocol corresponding to the first interface; and

a second controller configured to control communication according to a second protocol corresponding to the second interface;

wherein the first controller is coupled to differential data pins providing differential data signals, the differential data pins being coupled to the first and second communication conductors;

a first switch coupled between a first of the differential data pins and the first communication conductor, the controller component being configured to selectively close the first switch when the interface detection component provides the connection output indicative of the detected interface being the first interface;

a second switch coupled between a second of the differential data pins and the second communication conductor, the controller component being configured to selectively close the second switch when the interface detection component provides the connection output indicative of the detected interface being the first interface, wherein the controller component is configured to open the second switch when the interface detection component provides the connection output indicative of the detected interface being the second interface; and

wherein the second controller is configured to provide a high impedance signal on first and second I/O pins when the interface detection component provides the connection output indicative of the detected interface being the first interface.

2. The peripheral device of claim 1 and further comprising:

first and second resistive elements coupled between the first and second communication conductors and third and fourth I/O pins, respectively.

3. The peripheral device of claim 2 wherein the controller component provides a signal on the third and fourth I/O pins at a high impedance state when the interface detection component provides the connection output indicative of the detected interface being the first interface.

4. The peripheral device of claim 2 wherein the controller component provides a signal on the third and fourth I/O pins at a given voltage level when the interface detection component provides the connection output indicative of the detected interface being the second interface.

5. The peripheral device of claim 1 wherein the second controller is coupled to the first and second I/O pins providing a first data signal and a clock signal.

6. The peripheral device of claim 5 wherein the first and second I/O pins are coupled to the first and second communication conductors, respectively.

7. The peripheral device of claim 1 wherein the interface detection component comprises:

a fifth resistive element configured so the first switch selectively couples the first communication conductor to a third voltage potential through the fifth resistive element.

8. The peripheral device of claim 7 wherein the interface detection component comprises:

a sixth resistive element configured to the second switch selectively couples the second communication conductor to the third voltage potential through the sixth resistive element.