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Swappable sets of partial-mapping tables in a flash-memory system with a command queue for combining flash writes

  • US 8,112,574 B2
  • Filed: 12/31/2008
  • Issued: 02/07/2012
  • Est. Priority Date: 02/26/2004
  • Status: Expired due to Fees
First Claim
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1. A partially-mapped flash-memory controller comprising:

  • a host interface coupled to a host and configured for receiving host commands and a host logical-sector address (LSA) for host data to be written to flash memory;

    a flash interface to a flash memory;

    an internal bus coupled to the flash interface;

    a host buffer, coupled to the internal bus, configured for buffering data to and from the host interface;

    a random-access memory (RAM) coupled to the internal bus;

    a processor configured for executing controller routines, the processor coupled to the internal bus;

    a page data buffer in the RAM, configured for storing a page of host data;

    a command queue in the RAM, configured for storing a plurality of queue entries, each queue entry configured for storing the host command and the host LSA;

    a partial logical-to-physical (L2P) mapping table in the RAM, the partial L2P mapping table having entries that each store a physical-block address (PBA) of a physical block in the flash memory;

    N sets of partial L2P mapping tables stored in the flash memory;

    wherein the partial L2P mapping table stores one set of entries identified by a stored set number, wherein the flash memory requires N sets of entries to map the flash memory, wherein N is a whole number of at least 64;

    wherein the host LSA has a set number, an entry number, a page number, and a sector number;

    wherein a selected entry in the partial L2P mapping table is usable for mapping to the physical block in the flash memory when the set number matches the stored set number, and the entry number selects the selected entry;

    a tracking table in the RAM, the tracking table receiving the set number and outputting a table PBA that locates one of the N sets of partial L2P mapping tables stored in the flash memory;

    wear-leveling counters that each indicate a number of erases of a different physical block in the flash memory;

    wherein the entries in the partial L2P mapping table each further comprise a plurality of page-resident bits, each page-resident bit identifying when a bit'"'"'s page identified by a bit'"'"'s page number from a bit'"'"'s host LSA has been written to the flash memory;

    a table miss routine, executed by the processor when the stored set number mis-matches the set number from the host LSA, configured for copying modified entries in the partial L2P mapping table to the flash memory, and configured for reading a new set from flash memory, the new set being one of the N sets of partial L2P mapping tables in flash memory, and configured for loading the new set to the partial L2P mapping table;

    wherein a first stored page number identifies a first page number of a first host LSA of data currently stored in the data buffer;

    wherein a first stored entry number identifies a first entry number of the first host LSA of data currently stored in the data buffer;

    a buffer miss routine, executed by the processor when the first stored page number mis-matches the page number from the host LSA, or when the first stored entry number mis-matches the entry number from the host LSA, the buffer miss routine moving data stored in the data buffer to an old physical block in the flash memory, the old physical block being identified by an old PBA read from an old entry in the partial L2P mapping table, the old entry being located by the first stored entry number,whereby the RAM stores one of N sets of mapping entries to partially map the flash memory and whereby page-resident bits are set in entries in the partial L2P mapping table.

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