Dynamic broadcast of configuration loads supporting multiple transfer formats

• US 8,112,668 B2
• Filed: 07/29/2009
• Issued: 02/07/2012
• Est. Priority Date: 07/29/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swoboda, Gary L.
• Primary Examiner(s): Ehne, Charles
• Application Number:
  US12/512,002
• Publication Number:
  US 20100031089A1
• Time in Patent Office: 923 Days
• Field of Search: 714/30, 714/726, 714/727, 714/731
• US Class Current: 714/30
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G01R 31/318538 Topological or mechanical aspects
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/36 Preventing errors by testing or debugging software
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

A method for dynamically broadcasting configuration information to controllers connected in a scan topology in a target system is provided in which a selection event followed by the configuration information is received from a signal line at each of the controllers, wherein the plurality of controllers are connected in parallel to the signal line and the configuration information is stored within each controller that matches a selection criteria following the selection event when the selection event initiates a selection sequence.

Claims

1. A method for dynamically broadcasting configuration information to a plurality of controllers connected in a scan topology in a target system, the method comprising:

receiving a selection event followed by the configuration information from a signal line at each of the plurality of controllers, wherein the plurality of controllers are connected in parallel to the signal line; and

storing the configuration information within each controller of the plurality of controllers that matches a selection criteria following the selection event when the selection event initiates a selection sequence.

2. The method of claim 1, further comprising qualifying initiation of the selection event with a bit pattern preceding the selection event.

3. The method of claim 1, where the selection event is created with a bit pattern.

4. The method of claim 1, wherein the selection event and the configuration information are transmitted together serially on the signal line.

5. The method of claim 4, wherein the signal line is connected to test mode select pins of the plurality of controllers.

6. The method of claim 1, further comprising placing the controller offline when the selection criteria does not match selection criteria of the controller.

7. The method of claim 6, wherein the selection criteria specifies a topology type and the selection criteria of the controller specifies a topology type of the controller.

8. The method of claim 1, wherein receiving a selection event comprises:

receiving a clock signal that transitions between a first logic state and a second logic state;

receiving a data signal that contains data synchronized with the clock signal;

detecting two or more edge transitions on the data signal while the clock signal is held at the first logic state;

counting a number of edge transitions on the data signal while the clock signal is held at the first logic state; and

determining a selection event based on the counted number of edge transitions on the data signal when the clock signal transitions to the second logic state.

9. The method of claim 8, wherein the edge transitions occur while the clock signal is held for an extended period of time.

10. The method of claim 8, wherein the edge transitions occur while the clock signal continues to operate in a constant periodic manner.

11. A digital system, comprising:

at least one functional component with a controller, the controller comprising;

a clock input and a control input configured to receive test signals from a debug test system or other source;

a controller scan path having one or more bits, the controller scan path connected to a data input and a data output, wherein the data input and the data output are configured to be coupled to a scan path of a scan topology;

one or more global registers operable to store configuration information for the controller, and

control logic coupled to the global registers, the control logic configured to detect a selection event to initiate a selection sequence when selection criteria received with the selection event matches selection criteria of the controller, and further configured to store information within the selection sequence into the global registers when the selection criteria matches the selection criteria of the controller.

12. The digital system of claim 11, wherein the selection event and the selection criteria are received together serially.

13. The digital system of claim 11, wherein the control logic is further configured to receive and detect a bit pattern that determines whether the selection sequence is initiated by the selection event.

14. The digital system of claim 11, wherein the control logic is further configured to receive and detect a bit pattern that is detected as the selection event, wherein the selection sequence is initiated by the selection event.

15. The digital system of claim 11, wherein the control logic is further configured to place the controller in an offline mode when a selection sequence is initiated and the received selection criteria does not match the selection criteria of the controller, and to place the controller in an online mode when the received selection criteria matches the selection criteria of the controller.

16. The digital system of claim 11, wherein the scan topology in which the controller is deployed is either hardwired or recorded as a topology deployment value, and wherein the control logic is further configured to cause the controller to operate as a series connected device when the topology deployment value indicates the data input and the data output are coupled in series with the topology scan path, to operate as a four-wire parallel connected device when the topology deployment value indicates the data input and the data output are connected in parallel with the topology scan path, and to operate as a two-wire parallel connected device when the topology deployment value indicates the data input and data output are not connected to the topology scan path.

17. A digital system, comprising:

at least one functional component with a controller, the controller comprising;

a clock input and a data input configured to receive test signals from a debug test system or other source;

a controller scan path having one or more bits, the controller scan path connected to a data input;

one or more global registers operable to store configuration information for the controller; and

control logic coupled to the global registers, the control logic configured to detect a selection event and an selection criteria received on the data input, and further configured to configure the global registers to receive configuration information sent with the selection event and selection criteria when the selection criteria matches selection criteria of the controller.

18. The digital system of claim 17, wherein the selection event and the selection criteria are received together serially.

19. The digital system of claim 17, wherein the control logic is further configured to receive and detect a bit pattern that is detected as the selection event, wherein a selection sequence is initiated by the selection event.

20. The digital system of claim 17, wherein the control logic is further configured to place the controller in an offline mode when the received selection criteria does not match the selection criteria of the controller, and to place the controller in an online mode when the received selection criteria matches the selection criteria of the controller.

21. The digital system of claim 19, where information in the selection sequence determines the protocol the controller operates with following the selection sequence.