Error correction for programmable logic integrated circuits

• US 8,112,678 B1
• Filed: 12/13/2007
• Issued: 02/07/2012
• Est. Priority Date: 01/27/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Lewis, David, Betz, Vaughn
• Primary Examiner(s): Riad, Amine
• Application Number:
  US11/955,910
• Time in Patent Office: 1,517 Days
• Field of Search: 714/48
• US Class Current: 714/48
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing

Abstract

Systems and methods for detecting and correcting errors in programmable logic ICs are provided. In one embodiment, a scrubber periodically reads the memory cells in a programmable logic IC, detects and corrects any errors, and writes the corrected contents back into the memory cell. In another embodiment, regions of memory cells in a programmable logic IC each have associated error correcting circuitry which operates to continuously detect and correct errors as they occur. Error correcting circuitry can further be designed to reduce static hazards. It may be more desirable to design programmable logic IC routing architectures that reduce the number of memory cells needed to implement a given function. Error correcting circuitry can be provided for configuration memory or for an embedded memory block on a programmable logic IC.

Claims

1. A circuit that corrects errors in configuration data stored on a programmable logic integrated circuit device, the circuit comprising:

memory including memory cells on the programmable logic integrated circuit device, in which the configuration data are stored, and memory cells on the programmable logic integrated circuit device, in which error check data associated with the configuration data are stored; and

error correction circuitry coupled to at least some of the memory to analyze the configuration data stored in the memory to determine if any values have changed after initial storage of the configuration data in the memory and to correct any values that have changed, wherein the error correction circuitry comprises at least one scrubbing circuit operative to;

read from the memory a portion of the configuration data and an associated portion of the error check data; and

apply an error correcting code on the portion of the configuration data and the associated portion of the error check data to determine whether at least one bit in the portion of the configuration data has an error and to correct the at least one bit that has the error.

2. The circuit of claim 1 wherein the scrubbing circuit is associated with a subset of the configuration data and an associated subset of the error check data.

3. A digital processing system comprising:

processing circuitry;

another memory coupled to the processing circuitry; and

the programmable logic integrated circuit device having the circuit that corrects errors as defined in claim 1 coupled to the processing circuitry and the another memory.

4. A printed circuit board on which is mounted the programmable logic integrated circuit device having a circuit that corrects errors as defined in claim 1.

5. The printed circuit board defined in claim 4 further comprising:

another memory mounted on the printed circuit board and coupled to the programmable logic integrated circuit device.

6. The printed circuit board defined in claim 4 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the programmable logic integrated circuit device.

7. A circuit that corrects errors in configuration data stored on a programmable logic integrated circuit device, the circuit comprising:

memory including memory cells on the programmable logic integrated circuit device, in which the configuration data are stored, and memory cells on the programmable logic integrated circuit device, in which error check data associated with the configuration data are stored; and

at least one scrubber coupled to the memory and operative to;

read from the memory a portion of the configuration data and an associated portion of the error check data, and

apply an error correcting code on the portion of the configuration data and the portion of the error check data to determine whether at least one bit in the portion of the configuration data has an error and to correct the at least one bit that has the error.

8. The circuit of claim 7 further comprising one scrubber associated with the portion of the configuration data and the associated portion of the error check data.

9. The circuit of claim 7 further comprising more than one scrubber each associated with a subset of the portion of the configuration data and an associated subset of the associated portion of the error check data.

10. The circuit of claim 7 wherein the error correcting code is one of a Hamming Code, a Reed-Solomon Code, and a Product Code.

11. A method for correcting errors in configuration data stored on a programmable logic integrated circuit device, the method comprising:

generating error check data associated with the configuration data and storing the error check data in memory including memory cells on the programmable logic integrated circuit device, in which the configuration data are stored, and memory cells on the programmable logic integrated circuit device, in which error check data associated with the configuration data are stored;

reading a portion of the configuration data and an associated portion of the error check data;

determining if an error has occurred based on the portion of the configuration data and the associated portion of the error check data, wherein the determining comprises applying an error correcting code on the portion of the configuration data and the associated portion of the error check data; and

correcting the portion of the configuration data in response to the determining.

12. The method of claim 11 wherein the portion of the configuration data comprises at least one representative column of cells in the memory.

13. The method of claim 11 wherein the portion of the configuration data comprises at least one partial representative column of cells in the memory.

14. The method of claim 11 wherein the portion of the configuration data comprises at least two partial representative columns of cells in the memory that are physically contiguous.

15. The method of claim 11 wherein the error correcting code is one of a Hamming Code, a Reed-Solomon Code, and a Product Code.

16. The method of claim 11 wherein the correcting comprises writing the corrected portion of the configuration data into the memory.

17. A method for correcting errors in configuration data stored on a programmable logic integrated circuit device, the method comprising:

computing a first parity on each representative row of memory cells on the programmable logic integrated circuit device, in which the configuration data are stored; and

computing a second parity on each representative column of memory cells on the programmable logic integrated circuit device, in which the configuration data are stored;

wherein;

a parity bit associated with a respective one of each representative row and each representative column of memory cells on the programmable logic integrated circuit device is stored in a respective memory cell on the programmable logic integrated circuit device as error check data associated with the respective one of the representative row and the representative column of configuration data;

said method further comprising;

determining in parallel if an error has occurred in a cell associated with a respective one of each representative row and each representative column based on the first parity and the second parity; and

correcting the configuration data in the cell in response to the determining.

18. The method of claim 17 wherein the parity bit associated with each representative row and each representative column is a logic value that allows the associated representative row or representative column to have one of even parity and odd parity.

19. The method of claim 17 wherein correcting the configuration data comprises inverting the logic of the configuration data in the cell for output.

20. The method of claim 17 wherein correcting the configuration data comprises writing the corrected configuration data into the cell.

21. A method for correcting errors in configuration data stored on a programmable logic integrated circuit device, the method comprising:

computing a first parity on all but one cell in each representative row of memory cells on the programmable logic integrated circuit device; and

computing a second parity on all but the one cell in each representative column of memory cells on the programmable logic integrated circuit device;

wherein;

a parity bit associated with a respective one of each representative row and each representative column of memory cells on the programmable logic integrated circuit device is stored in a respective memory cell on the programmable logic integrated circuit device as error check data associated with the respective one of the representative row and the representative column of configuration data;

said method further comprising;

determining in parallel if an error has occurred in the one cell associated with a respective one of each representative row and each representative column based on the first parity, the second parity, and configuration data in the one cell; and

generating a correct value for the configuration data in the one cell based on the first parity, the second parity, and the configuration data in the one cell.

22. The method of claim 21 wherein the parity bit associated with each representative row and each representative column is a logic value that allows the associated representative row or representative column to have one of even parity and odd parity.

23. The method of claim 21 further comprising writing the corrected configuration data into the one cell.