Switched resonant ultrasonic power amplifier system
First Claim
1. A system for controlling an output of an ultrasonic device, the system comprising:
- an amplifier that receives and processes a driver output signal and generates a drive signal to control output of the ultrasonic device;
an output control circuit that receives and processes a signal related to a feedback signal generated by the ultrasonic device and a divider reference signal that generates a compensated clock signal that is adjusted for at least one of phase and frequency differences between the received feedback signal and the divider reference signal;
a compensated drive circuit receives and processes the compensated clock signal and generates the divider reference signal, and that generates the driver output signal;
the output control circuit further including a compensating circuit operatively coupled to the compensated drive circuit, the compensating circuit having a phase locked loop (PLL);
the output control circuit further including a wave shaping circuit that receives and processes the feedback signal and generates a square wave reset signal having a frequency substantially identical to the feedback signal;
the compensating circuit receiving and processing the reset signal for generating a compensated reference signal having substantially the same frequency as the reset signal substantially 180°
out-of-phase with respect to the reset signal, wherein frequency and amplitude characteristics of the compensated reference signal are determined at least by the reset signal; and
the PLL receiving and processing first and second input signals, wherein the first input signal is the compensated reference signal and the second input signal is the divider reference signal, and wherein the PLL processes the first and second input signals and generates the compensated clock signal.
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Abstract
A switched resonant power amplifier system for ultrasonic transducers is disclosed. The system includes an amplifier that receives and processes a driver output signal for generating a drive signal that is provided to an ultrasonic device for controlling output of the ultrasonic device. An output control circuit receives and processes a signal related to a feedback signal generated by the ultrasonic device and a divider reference signal, and generates a compensated clock signal that is adjusted for at least one of phase and frequency differences between the received feedback signal and the divider reference signal. A compensated drive circuit receives and processes the compensated clock signal for generating the divider reference signal, and for generating the driver output signal.
803 Citations
18 Claims
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1. A system for controlling an output of an ultrasonic device, the system comprising:
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an amplifier that receives and processes a driver output signal and generates a drive signal to control output of the ultrasonic device; an output control circuit that receives and processes a signal related to a feedback signal generated by the ultrasonic device and a divider reference signal that generates a compensated clock signal that is adjusted for at least one of phase and frequency differences between the received feedback signal and the divider reference signal; a compensated drive circuit receives and processes the compensated clock signal and generates the divider reference signal, and that generates the driver output signal; the output control circuit further including a compensating circuit operatively coupled to the compensated drive circuit, the compensating circuit having a phase locked loop (PLL); the output control circuit further including a wave shaping circuit that receives and processes the feedback signal and generates a square wave reset signal having a frequency substantially identical to the feedback signal; the compensating circuit receiving and processing the reset signal for generating a compensated reference signal having substantially the same frequency as the reset signal substantially 180°
out-of-phase with respect to the reset signal, wherein frequency and amplitude characteristics of the compensated reference signal are determined at least by the reset signal; andthe PLL receiving and processing first and second input signals, wherein the first input signal is the compensated reference signal and the second input signal is the divider reference signal, and wherein the PLL processes the first and second input signals and generates the compensated clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification