Phase change material based temperature sensor

• US 8,114,686 B2
• Filed: 06/21/2010
• Issued: 02/14/2012
• Est. Priority Date: 06/29/2007
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Habib, Nazmul, Lam, Chung Hon, McMahon, Robert
• Primary Examiner(s): Tran, Long
• Assistant Examiner(s): KLEIN, JORDAN M
• Application Number:
  US12/819,721
• Publication Number:
  US 20100254425A1
• Time in Patent Office: 603 Days
• Field of Search: 438/14, 438/17, 438/18, 257467-470, 257/E21.068, 257/E45.002, 374/21
• US Class Current: 438/14
• CPC Class Codes: G01K 11/06 using melting, freezing, or softening
• CPC Class Codes: G01K 7/16 using resistive elements resistive elements per se H01C, H01L
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/884 based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883

Abstract

A block of phase change material located in a semiconductor chip is reset to an amorphous state. The block of phase change material may be connected to an internal resistance measurement circuit that can transmit the measured resistance data to input/output pads either in an analog output format or in a digital output format. Depending on the ambient temperature, the resistance of the block of phase change material changes. By measuring a fractional resistance change compared to the resistance of the phase change material at a calibration temperature, the temperature of the region around the phase change material can be accurately measured. A logic decoder and an input/output circuit may be employed between the internal resistance measurement circuit and the input/output pads. A plurality of temperature sensing circuits containing phase change material blocks may be employed in the semiconductor chip to enable an accurate temperature profiling during chip operation.

Claims

1. A method of measuring an operating temperature of a semiconductor chip comprising:

characterizing temperature dependency of the resistivity of an amorphous phase change material and generating a fitting function;

designing and manufacturing a semiconductor circuit having a block of said amorphous phase change material and current measurement capability through said block;

subjecting said semiconductor chip to an operating condition and measuring an operating condition current through said block;

calculating an operation condition resistivity from said measured operating condition current; and

calculating a temperature at which said fitting function generates said calculated operating condition resistivity, wherein said semiconductor circuit includes a semiconductor structure comprising;

a semiconductor device including a component located within a semiconductor substrate, wherein said component comprises a same semiconductor material as said semiconductor substrate, said block of said amorphous phase change material contacting a surface of said component and embedded in a dielectric layer located over said semiconductor substrate;

a first metal contact that is in direct contact with one portion of said block and embedded in said dielectric layer; and

a second metal contact that is in direct contact with another portion of said block and embedded in said dielectric layer.

2. The method of claim 1, further comprising modifying said fitting function by matching said fitting function with a measured value of resistivity of said phase change material at a standard condition prior to calculating said temperature.

3. The method of claim 2, wherein said measured value of resistivity at said standard condition is derived from a standard condition current measurement through said block.

4. The method of claim 1, wherein said fitting function is a polynomial of temperature having at least one segment and defined below a crystallization temperature.

5. The method of claim 1, further comprising resetting said block to an amorphous state prior to said subjecting of said semiconductor chip to said operating condition.

6. The method of claim 1, wherein said semiconductor structure further comprises:

a metal wiring configured to enable measurement of a resistance of said block;

a sensing circuitry that includes a resistance measurement circuit that is connected to said metal wiring and is configured to measure a resistance of said block by measuring said current, wherein said sensing circuitry determines a local ambient temperature of said block based on said measured resistance during operation of said semiconductor chip.

7. The method of claim 1, wherein said block of phase change material contacts a top surface of a semiconductor component selected from the group consisting of source and drain regions, an emitter, a collector, a gate, a diode.

8. The method of claim 1, wherein said semiconductor device is a metal-oxide-semiconductor field effect transistor (MOSFET).

9. The method of claim 8, wherein said component is a source region or a drain region of said MOSFET.

10. A method of measuring an operating temperature of a semiconductor chip comprising:

characterizing temperature dependency of the resistivity of an amorphous phase change material and generating a fitting function;

designing and manufacturing a semiconductor circuit having a block of said amorphous phase change material and current measurement capability through said block;

subjecting said semiconductor chip to an operating condition and measuring an operating condition current through said block;

calculating an operation condition resistivity from said measured operating condition current; and

calculating a temperature at which said fitting function generates said calculated operating condition resistivity, wherein said semiconductor circuit as manufactured includes a semiconductor structure comprising;

a metal-oxide-semiconductor field effect transistor (MOSFET) located on a semiconductor substrate and including a gate dielectric that contacts a top surface of said semiconductor substrate;

said block of said amorphous phase change material contacting a surface of a semiconductor device component located within a semiconductor substrate and said block embedded in a dielectric layer located over said semiconductor substrate; and

another dielectric layer contacting an entirety of a bottom surface of said block of phase change material and electrically isolating said block of phase change material from any semiconductor device located directly underneath said block of phase change material.

11. The method of claim 10, further comprising modifying said fitting function by matching said fitting function with a measured value of resistivity of said phase change material at a standard condition prior to calculating said temperature.

12. The method of claim 11, wherein said measured value of resistivity at said standard condition is derived from a standard condition current measurement through said block.

13. The method of claim 10, wherein said fitting function is a polynomial of temperature having at least one segment and defined below a crystallization temperature.

14. The method of claim 10, further comprising resetting said block to an amorphous state prior to said subjecting of said semiconductor chip to said operating condition.

15. The method of claim 10, wherein said semiconductor structure further comprises:

a first metal contact that is in direct contact with one portion of said block and embedded in said dielectric layer; and

a second metal contact that is in direct contact with another portion of said block and embedded in said dielectric layer.

16. The method of claim 15, wherein said semiconductor structure further comprises:

a metal wiring configured to enable measurement of a resistance of said block;

a sensing circuitry that includes a resistance measurement circuit that is connected to said metal wiring and is configured to measure a resistance of said block by measuring said current, wherein said sensing circuitry determines a local ambient temperature of said block based on said measured resistance during operation of said semiconductor chip.

17. The method of claim 10, wherein said other dielectric layer is in direct contact with said top surface of said semiconductor substrate, wherein said other dielectric layer and said gate dielectric have a same composition and a same thickness.

18. The method of claim 17, wherein said other dielectric layer is in direct contact with a source region or a drain region of a MOSFET, and does not directly contact said gate dielectric.

19. The method of claim 18, wherein first metal contact and said second metal contact are in direct contact with a topmost surface of said block.