Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip

• US 8,114,707 B2
• Filed: 03/25/2010
• Issued: 02/14/2012
• Est. Priority Date: 03/25/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Farooq, Mukta G., Petrarca, Kevin S., Volant, Richard P.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US12/731,487
• Publication Number:
  US 20110237026A1
• Time in Patent Office: 691 Days
• Field of Search: 438/108, 438/107, 438/113, 438/458, 438/459, 438/464, 257/E21.499
• US Class Current: 438/107
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]

Abstract

A temporary substrate having an array of first solder pads is bonded to the front side of a first substrate by reflowing an array of first solder balls. The first substrate is thinned by removing the back side, and an array of second solder pads is formed on the back side surface of the first substrate. The assembly of the first substrate and the temporary substrate is diced to form a plurality of stacks, each including an assembly of a first semiconductor chip and a handle portion. A second semiconductor chip is bonded to an assembly through an array of the second solder balls. The handle portion is removed from each assembly by reflowing the array of the first solder balls, while the array of the second solder balls does not reflow. The assembly is subsequently mounted on a packaging substrate employing the array of the first solder balls.

Claims

1. A method of forming a multi-chip assembly of semiconductor chips comprising:

forming a stacked substrate assembly by bonding a semiconductor substrate to a temporary substrate through an array of first solder balls that bonds to an array of first solder pads on said semiconductor substrate;

dicing said stacked substrate assembly to form a plurality of stacked temporary structures, each of said plurality of stacked temporary structures comprising a first semiconductor chip that is a portion of said semiconductor substrate and a handle portion that is a portion of said temporary substrate;

bonding a second semiconductor chip to a stacked temporary structure among said plurality of stacked temporary structures, wherein an array of second solder balls is bonded to an array of second solder pads located on a first semiconductor chip in said stacked temporary structure and an array of third solder pads located on said second semiconductor chip;

detaching a handle portion from said stacked temporary structure to form a stacked semiconductor chip structure; and

forming a multi-chip assembly of semiconductor chips by bonding at least one stacked semiconductor chip structure including said stacked semiconductor chip structure to a packaging substrate.

2. The method of claim 1, wherein said stacked semiconductor chip structure comprises, from top to bottom, said second semiconductor chip, said array of third solder pads, said array of second solder balls, said array of second solder pads, a first semiconductor chip, a portion of said array of first solder pads, and a portion of said array of first solder balls.

3. The method of claim 1, wherein said stacked semiconductor chip structure is bonded to said packaging substrate through a portion of said array of said first solder balls.

4. The method of claim 3, further comprising forming an array of package-side bonding pads on a surface of said packaging substrate, wherein said stacked semiconductor chip structure is bonded to said packaging substrate through a portion of said array of first solder balls that is bonded to said array of package-side bonding pads and to a portion of said array of first solder pads on a first semiconductor chip in said stacked semiconductor chip structure.

5. The method of claim 3, further comprising bonding another stacked semiconductor chip structure to said packaging substrate, wherein said stacked semiconductor chip structure comprises, from top to bottom, said second semiconductor chip, said array of third solder pads, said array of second solder balls, said array of second solder pads, a first semiconductor chip, a portion of said array of first solder pads, and a portion of said array of first solder balls, and wherein said other stacked semiconductor chip structure comprises, from top to bottom, another second semiconductor chip, another array of third solder pads, another array of second solder balls, another array of second solder pads, another first semiconductor chip, another portion of said array of first solder pads, and another portion of said array of first solder balls.

6. The method of claim 1, wherein said semiconductor substrate includes a stack of a metal interconnect structure layer and a semiconductor layer, wherein said array of first solder pads is formed directly on an outer surface of said metal interconnect structure layer.

7. The method of claim 1, further comprising thinning said semiconductor substrate while said temporary substrate is bonded to said semiconductor substrate and before said dicing.

8. The method of claim 7, wherein said array of second solder pads is formed on a surface of a thinned semiconductor layer after said thinning and prior to said dicing.

9. The method of claim 1, further comprising forming an array of conductive studs in a semiconductor layer in said semiconductor substrate prior to said bonding of said semiconductor substrate to said temporary substrate, wherein said array of said conductive studs extends at least from an interface between said semiconductor layer and a metal interconnect structure layer to a depth into said semiconductor layer.

10. The method of claim 9, further comprising thinning said semiconductor layer while said temporary substrate is bonded to said semiconductor substrate and before said dicing, wherein said array of said conductive studs constitute an array of through-substrate vias (TSVs) extending at least from said interface to an exposed surface of said semiconductor layer after said thinning.

11. The method of claim 10, wherein said array of said second solder pads is formed directly on said exposed surface of said semiconductor layer after said thinning.

12. The method of claim 1, wherein said semiconductor substrate includes a stack of a first semiconductor layer and a first metal interconnect structure layer, said second semiconductor chip includes a stack of a second semiconductor layer and a second metal interconnect layer, said array of said first solder pads is formed directly on said first metal interconnect structure layer, and said array of said third solder pads is formed directly on said second metal interconnect structure layer.

13. The method of claim 12, wherein said array of said second solder pads is formed directly on a surface of said first semiconductor layer and does not contact said first metal interconnect structure layer.

14. The method of claim 12, wherein said first semiconductor layer comprises at least one first semiconductor device and said second semiconductor layer comprises at least one second semiconductor device.

15. The method of claim 14, wherein said temporary substrate does not include any semiconductor device.

16. The method of claim 1, wherein a first semiconductor chip and a handle portion within said stacked temporary structure have horizontal cross-sectional shapes that are congruent with each other.

17. The method of claim 1, wherein said array of said first solder balls is composed of a first solder material, and said array of said second solder balls is composed of a second solder material, wherein said first solder material has a lower reflow temperature than said second solder material.

18. The method of claim 1, further comprising forming an array of solder pads on said temporary substrate, wherein a contact area with a solder pad in said array of solder pads is smaller than a contact area with a first solder pad in said array of said first solder pads for each first solder ball in said array of first solder balls.

19. The method of claim 1, further comprising:

forming a first dielectric underfill layer between said first semiconductor chip and said second semiconductor chip; and

forming a second dielectric underfill layer between said first semiconductor chip and said packaging substrate.

20. The method of claim 1, wherein said packaging substrate is a ceramic packaging substrate or a laminate packaging substrate, said first semiconductor chip is a processor chip, and said second semiconductor chip is a static random access memory (SRAM) chip, a dynamic random access memory (DRAM) chip, or a non-volatile memory chip.