Semiconductor device and manufacturing method thereof

• US 8,114,720 B2
• Filed: 12/09/2009
• Issued: 02/14/2012
• Est. Priority Date: 12/25/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): DUONG, KHANH B
• Application Number:
  US12/634,048
• Publication Number:
  US 20100167464A1
• Time in Patent Office: 797 Days
• Field of Search: None
• US Class Current: 438/149
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a first conductive layer over a substrate;

selectively forming a resist mask with plural thicknesses over the first conductive layer;

etching the first conductive layer by using the resist mask to form a gate electrode and a first wiring;

removing the resist mask over the gate electrode and leaving part of the resist mask over the first wiring;

forming a gate insulating layer so as to cover the gate electrode, the first wiring, and the resist mask;

forming a second conductive layer over the gate insulating layer;

selectively etching the second conductive layer to form a source and drain electrodes, and to form a second wiring overlapping the first wiring; and

forming a semiconductor layer in contact with the source and drain electrodes in a region overlapped with the gate electrode.

2. A method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is an oxide semiconductor layer containing indium, gallium, and zinc.

3. A method for manufacturing a semiconductor device according to claim 1, wherein the first wiring is formed so that a width of the first wiring in a region overlapped with the resist mask is smaller than a width of the first wiring in other regions.

4. A method for manufacturing a semiconductor device according to claim 1, wherein the second wiring is formed so that a width of the second wiring in a region overlapped with the resist mask is smaller than a width of the second wiring in other regions.

5. A method for manufacturing a semiconductor device according to claim 1, wherein the first wiring is formed so that a thickness of the first wiring in a region overlapped with the resist mask is larger than a thickness of the first wiring in other regions.

6. A method for manufacturing a semiconductor device according to claim 1, further comprising a conductive layer over the second wiring in the region overlapped with the resist mask.

7. A method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is one selected from the group consisting of a poster, an advertisement, an electronic book, a television set, a digital photo frame, a game machine and a phone.

8. A method for manufacturing a semiconductor device, comprising:

forming a first conductive layer over a substrate;

selectively forming a resist mask over the first conductive layer;

etching the first conductive layer by using the resist mask to form a gate electrode and a first wiring;

removing the resist mask over the gate electrode and the first wiring;

forming an insulating layer over the first wiring;

forming a gate insulating layer so as to cover the gate electrode, the first wiring, and the insulating layer;

forming a second conductive layer over the gate insulating layer;

selectively etching the second conductive layer to form a source and drain electrodes, and to form a second wiring overlapping the first wiring; and

forming a semiconductor layer in contact with the source and drain electrodes in a region overlapped with the gate electrode.

9. A method for manufacturing a semiconductor device according to claim 8, wherein the semiconductor layer is an oxide semiconductor layer containing indium, gallium, and zinc.

10. A method for manufacturing a semiconductor device according to claim 8, wherein the first wiring is formed so that a width of the first wiring in a region overlapped with the resist mask is smaller than a width of the first wiring in other regions.

11. A method for manufacturing a semiconductor device according to claim 8, wherein the second wiring is formed so that a width of the second wiring in a region overlapped with the resist mask is smaller than a width of the second wiring in other regions.

12. A method for manufacturing a semiconductor device according to claim 8, wherein the first wiring is formed so that a thickness of the first wiring in a region overlapped with the resist mask is larger than a thickness of the first wiring in other regions.

13. A method for manufacturing a semiconductor device according to claim 8, further comprising a conductive layer over the second wiring in the region overlapped with the resist mask.

14. A method for manufacturing a semiconductor device according to claim 8, wherein the semiconductor device is one selected from the group consisting of a poster, an advertisement, an electronic book, a television set, a digital photo frame, a game machine and a phone.

15. A method for manufacturing a semiconductor device, comprising:

forming a first conductive layer over a substrate;

selectively forming a resist mask over the first conductive layer;

etching the first conductive layer by using the resist mask to form a gate electrode and a first wiring;

removing the resist mask over the gate electrode and the first wiring;

forming a gate insulating layer so as to cover the gate electrode and the first wiring;

forming an insulating layer over the gate insulating layer;

forming a second conductive layer over the insulating layer;

forming a first semiconductor layer over the second conductive layer;

selectively etching the first semiconductor layer, the second conductive layer and the insulating layer to form a source and drain electrodes, and to form a second wiring overlapping the first wiring; and

forming a second semiconductor layer in contact with the source and drain electrodes in a region overlapped with the gate electrode.

16. A method for manufacturing a semiconductor device according to claim 15, wherein the second semiconductor layer is an oxide semiconductor layer containing indium, gallium, and zinc.

17. A method for manufacturing a semiconductor device according to claim 15, wherein the first wiring is formed so that a width of the first wiring in a region overlapped with the resist mask is smaller than a width of the first wiring in other regions.

18. A method for manufacturing a semiconductor device according to claim 15, wherein the second wiring is formed so that a width of the second wiring in a region overlapped with the resist mask is smaller than a width of the second wiring in other regions.

19. A method for manufacturing a semiconductor device according to claim 15, wherein the first wiring is formed so that a thickness of the first wiring in a region overlapped with the resist mask is larger than a thickness of the first wiring in other regions.

20. A method for manufacturing a semiconductor device according to claim 15, further comprising a conductive layer over the second wiring in the region overlapped with the resist mask.

21. A method for manufacturing a semiconductor device according to claim 15, wherein the semiconductor device is one selected from the group consisting of a poster, an advertisement, an electronic book, a television set, a digital photo frame, a game machine and a phone.