Profile of flash memory cells

• US 8,114,740 B2
• Filed: 03/11/2011
• Issued: 02/14/2012
• Est. Priority Date: 03/07/2007
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Shih-Chang, Chang, Chu-Wei, Lo, Chi-Hsin, Tsai, Chia-Shiung
• Primary Examiner(s): Bryant, Kiesha
• Assistant Examiner(s): Anya, Igwe U
• Application Number:
  US13/045,955
• Publication Number:
  US 20110165746A1
• Time in Patent Office: 340 Days
• Field of Search: 438/264
• US Class Current: 438/264
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.

Claims

1. A method comprising:

forming a tunneling layer over a semiconductor substrate;

forming a source region adjacent the tunneling layer;

forming a floating gate over the tunneling layer;

forming a blocking layer over the floating gate, wherein the blocking layer has a first edge facing a same direction as a first edge of the floating gate;

forming a control gate over the blocking layer; and

recessing the first edge of the blocking layer until the first edge of the blocking layer is recessed from an edge of the control gate facing the same direction.

2. The method of claim 1 further comprising recessing the first edge of the floating gate until the first edge of the floating gate comprises an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion.

3. The method of claim 2, wherein the floating gate comprises polysilicon, and wherein the step of recessing the floating gate comprises etching an edge portion of the floating gate using chlorine and HBr.

4. The method of claim 3, wherein during the step of etching the edge portion of the floating gate, a ratio of a flow rate of chlorine to a flow rate of HBr is greater than ⅕

.

5. The method of claim 2, wherein the lower portion of the floating gate is recessed from the upper portion by a distance greater than about 10 percent of a width of the floating gate.

6. The method of claim 1, wherein the first edges of the floating gate and the blocking layer face the source region.

7. The method of claim 1, wherein the steps of forming the tunneling layer and the floating gate comprise:

forming shallow trench isolation (STI) regions in the semiconductor substrate, wherein the STI regions have top surfaces higher than a top surface of the semiconductor substrate;

thermal oxidizing the top surface of the semiconductor substrate to form the tunneling layer;

blanket forming a floating gate layer over the STI regions and the semiconductor substrate; and

performing a chemical mechanical polish to remove portions of the floating gate layer over the STI regions, wherein a remaining portion of the floating gate layer forms the floating gate.

8. The method of claim 1, wherein the first edge of the floating layer is recessed from the first edge of the blocking layer.

9. The method of claim 1, wherein the floating gate further comprises a second, a third, and a fourth edge, and wherein the second, the third, and the fourth edges are substantially vertical.

10. A method comprising:

forming shallow trench isolation (STI) regions in a semiconductor substrate, wherein the STI regions define;

a strip of active region in the semiconductor substrate; and

a connecting active region perpendicular to the strip of active region and separating the strip of active region into a first active region and a second active region;

forming a first tunneling layer over the first active region and a second tunneling layer over the second active region;

forming a first floating gate leg over the first tunneling layer;

forming a second floating gate leg over the second tunneling layer;

forming a connecting floating gate portion over the connecting active region and connecting the first and the second floating gate legs; and

etching the connecting floating gate portion to form a first floating gate and a second floating gate, wherein each of the first floating gate and the second floating gate comprises a first edge facing the connecting active region, and wherein each of the first edges of the first floating gate and the second floating gate comprise a lower portion and an upper portion, with the lower portion recessed from the upper portion.

11. The method of claim 10 further comprising:

forming a first and a second blocking layer over the first and the second floating gate legs, respectively; and

forming a control gate over the first blocking layer, wherein during the step of etching the connecting floating gate portion, an edge of the first blocking layer is recessed from a respective edge of the control gate, with the respective edge of the control gate facing a same direction as the first edge of the first floating gate.

12. The method of claim 11, wherein each of the first and the second blocking layers comprises a portion extending directly over an edge of the connecting active region, and wherein the step of removing the connecting floating gate portion comprises over-etching the floating gate portion until the first and the second floating gates are spaced apart from the edge of the connecting active region.

13. The method of claim 10, wherein the lower portion of each of the first and the second floating gates is recessed from the respective upper portion by a distance greater than about 10 percent of a width of a respective one of the first and second floating gates.

14. The method of claim 10, wherein each of the first and the second floating gates further comprises a second, a third, and a fourth edge, and wherein the second, the third, and the fourth edges are substantially vertical.

15. The method of claim 10, wherein the steps of forming the first and the second floating gate legs and the connecting floating gate portion comprise:

blanket forming a floating gate layer over the STI regions and the semiconductor substrate; and

performing a chemical mechanical polish to remove portions of the floating gate layer over the STI regions.

16. A method comprising:

forming a tunneling layer over a semiconductor substrate;

forming a source region adjacent the tunneling layer;

forming a floating gate over the tunneling layer;

forming a blocking layer over the floating gate;

forming a control gate over the blocking layer; and

over-etching an edge of the floating gate and an edge of the blocking layer facing a same direction until the edge of the blocking layer is recessed from an edge of the control gate facing the same direction and until the edge of the floating gate is recessed from the edge of the blocking layer.

17. The method of claim 16, wherein the edge of the floating gate comprises an upper portion and a lower portion, and wherein after the step of over-etching, the lower portion is recessed from the upper portion.

18. The method of claim 16, wherein the edges of the floating gate and the blocking layer face the source region.

19. The method of claim 16, wherein the floating gate comprises polysilicon, and wherein the step of over-etching is performed using an etchant comprising chlorine and HBr, with a ratio of a flow rate of chlorine to a flow rate of HBr being greater than about ⅕

.