Nonvolatile semiconductor memory and method of manufacturing the same

• US 8,114,742 B2
• Filed: 05/11/2011
• Issued: 02/14/2012
• Est. Priority Date: 10/04/2007
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kikuchi, Takeshi
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US13/067,141
• Publication Number:
  US 20110217831A1
• Time in Patent Office: 279 Days
• Field of Search: 438/261, 438/267
• US Class Current: 438/267
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A method of forming a nonvolatile memory device which includes forming a first gate electrode on a gate insulating film formed on a semiconductor substrate. The first gate electrode having a lower portion formed on the gate insulating film and an upper portion having a gate length less than that of the lower portion formed on the lower portion. A spacer is formed contacting surfaces of the upper and lower portions, wherein a length of the spacer and the upper portion equals the length of the lower portion. An electric charge trapping film covers a portion of the semiconductor substrate, a surface of the lower portion, and a surface of the spacer. A second gate electrode is then formed in a side direction of the first gate electrode and electrically insulated from the first gate electrode by the electric charge trapping film. The second gate electrode has a distance between the upper portion of the first gate electrode thai is greater than a distance between the lower portion and is separated from the upper portion of the first gate electrode by the electric charge trapping film and the spacer.

Claims

1. A method of forming a nonvolatile semiconductor memory device, said method comprising:

forming a semiconductor substrate;

forming upper and lower portions of a first gate electrode on a gate insulating film formed on said semiconductor substrate, said lower portion of said first gate electrode formed on said gate insulating film, said upper portion of said first gate electrode formed on said lower portion of said first gate electrode and having a gate length which is less than a gate length of said lower portion of said first gate electrode;

forming a spacer insulating film to contact respective surfaces of the upper and lower portions of said first gate electrode, a length of said spacer insulating film combined with the gate length of the upper portion of said first gate electrode being equal to said gate length of said lower portion of said first gate electrode;

forming an electric charge trapping film covering a portion of the semiconductor substrate, a surface of the lower portion of the first gate electrode, and a surface of the spacer insulating film; and

forming a second gate electrode in a side direction of said first gate electrode and electrically insulated from said first gate electrode by said electric charge trapping film, said second gate electrode having a distance between said upper portion of said first gate electrode that is greater than a distance between said lower portion of said first gate electrode and said second gate electrode, said second gate electrode being separated from said upper portion of said first gate electrode by said electric charge trapping film and said spacer insulating film.

2. The method according to claim 1, wherein a section shape of said first gate electrode in a plane that is perpendicular to said semiconductor substrate and perpendicular to a direction in which said first gate electrode extends on a surface of said semiconductor substrate includes a convex shape.

3. The method according to claim 1, further comprising:

forming a silicide layer covering a surface of said upper portion of said first gate electrode.

4. The method according to claim 1, wherein a distance between said semiconductor substrate and a surface of said upper portion of said first gate electrode is greater than a distance between said semiconductor substrate and all surfaces of said second gate electrode.

5. The method according to claim 1, wherein a distance between said semiconductor substrate and all surfaces of said upper portion of said first gate electrode is less than a distance between said semiconductor substrate and a surface of said second gate electrode.

6. The method according to claim 1, wherein said distance between said lower portion of said first gate electrode and said second gate electrode is equal to a distance between said second gate electrode and said spacer insulating film.

7. The method according to claim 1, further comprising:

forming a silicide layer that abuts a surface of said upper portion of said first gate electrode.

8. The method according to claim 1, wherein said electric charge trapping film has an L-shape.