Semiconductor wafer scale package system

• US 8,114,771 B2
• Filed: 12/22/2006
• Issued: 02/14/2012
• Est. Priority Date: 01/13/2006
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Jeon, Hyung Jun, Lee, Tae Keun, Ko, Young Chan
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): AHMED, SELIM U
• Application Number:
  US11/615,923
• Publication Number:
  US 20070164422A1
• Time in Patent Office: 1,880 Days
• Field of Search: 438/667, 438/108, 257/698, 257/E23.174
• US Class Current: 438/667
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/72 Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor wafer scale package system is provided including providing a semiconductor substrate having a through-hole via with a conductive coating, forming a filled via by filling the through-hole via with a conductive material, coupling a package substrate to the filled via, and singulating a chip scale package from the semiconductor substrate and the package substrate.

Claims

1. A semiconductor wafer scale packaging method comprising:

providing a semiconductor substrate, with an active side and a backside, having a through-hole via lined with a conductive coating, to fill the opening at the active side, formed directly on the semiconductor substrate;

forming a filled via by filling the through-hole via with a conductive material;

coupling a package substrate to the filled via including the active side away from the package substrate; and

singulating a chip scale package from the semiconductor substrate and the package substrate.

2. The method as claimed in claim 1 further comprising molding an encapsulant over the semiconductor substrate.

3. The method as claimed in claim 1 further comprising:

forming a semiconductor device on the semiconductor substrate having the active side;

forming a contact coupled to the semiconductor device on the active side; and

coupling the contact to the conductive coating in the through-hole via.

4. The method as claimed in claim 1 wherein filling the through-hole via with the conductive material including using a solder paste, a solder ball, or a curable adhesive.

5. The method as claimed in claim 1 further comprising:

forming a solder bump on a package substrate;

aligning the solder bump with the filled via; and

coupling the solder bump to the filled via with a reflow process.

6. A semiconductor wafer scale packaging method comprising:

providing a semiconductor substrate, with an active side and a backside, having a through-hole via lined with a conductive coating, to fill the opening at the active side, formed directly on the semiconductor substrate, including forming the through-hole via near the edge of a semiconductor device;

forming a filled via by filling the through-hole via with a conductive material including spraying or printing the conductive material;

coupling a package substrate to the filled via including the active side away from the package substrate by coupling all of the filled via on the semiconductor substrate to the package substrate; and

singulating a chip scale package from the semiconductor substrate and the package substrate including singulating the chip scale package.

7. The method as claimed in claim 6 further comprising:

molding an encapsulant over the semiconductor substrate including molding an epoxy molding compound; and

coupling system interconnects to the package substrate.

8. The method as claimed in claim 6 further comprising:

forming a semiconductor device on the semiconductor substrate having the active side;

forming a contact on the active side in which forming the contact includes forming the semiconductor device; and

coupling the contact to the conductive coating in the through-hole via in which coupling the contact includes electroplating the conductive coating.

9. The method as claimed in claim 6 wherein filling the through-hole via with the conductive material by using a solder paste a solder ball, or a curable adhesive includes using a eutectic, high temperature solder, or conductive epoxy for coupling the through-hole via to a central plane.

10. The method as claimed in claim 6 further comprising:

forming a solder bump on a package substrate including forming a solder ball or a solder column;

aligning the solder bump with the filled via including aligning the semiconductor substrate with the package substrate; and

forming a wafer scale package by coupling the solder bump to the filled via with a reflow process.