Array substrate and method for manufacturing the same
First Claim
1. An array substrate comprising:
- a substrate;
a gate metal layer disposed on the surface of the substrate and serving as a gate and a scan line;
a gate insulation layer disposed on the substrate and covering on the gate metal layer;
a semiconductor layer disposed on the surface of the gate insulation layer and over the gate;
a patterned metal layer disposed on the surface of the semiconductor layer and the surface of the gate insulation layer, wherein the patterned metal layer formed on the surface of the semiconductor layer comprises a source and a drain, the patterned metal layer formed on the surface of the gate insulation layer comprises a storage capacitor line and a data line, and the storage capacitor line has a main portion and an extending portion substantially perpendicular to the main portion, wherein the main portion is substantially parallel to the data line and the extending portion is substantially parallel to the scan line;
a flat layer covering over the substrate;
and a pixel electrode disposed on the surface of the flat layer, which connects with the drain, and overlapping parts of the scan line, parts of the data line, parts of the storage capacitor fine, and parts of the extending portion.
1 Assignment
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Accused Products
Abstract
An array substrate is disclosed. The array substrate comprises a substrate, a gate metal layer, a gate insulation layer, a semiconductor layer, a patterned metal layer, a flat layer, and a pixel electrode. The patterned metal layer is disposed on the surface of the semiconductor layer comprising a source and a drain, and on the surface of the gate insulation layer comprising a storage capacitor line and a data line. The storage capacitor line has an extending portion parallel to a scan line. The pixel electrode overlaps parts of the scan line, parts of the data line, parts of the storage capacitor line, and parts of the extending portion. A method for manufacturing the array substrate is also provided.
5 Citations
20 Claims
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1. An array substrate comprising:
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a substrate; a gate metal layer disposed on the surface of the substrate and serving as a gate and a scan line; a gate insulation layer disposed on the substrate and covering on the gate metal layer; a semiconductor layer disposed on the surface of the gate insulation layer and over the gate; a patterned metal layer disposed on the surface of the semiconductor layer and the surface of the gate insulation layer, wherein the patterned metal layer formed on the surface of the semiconductor layer comprises a source and a drain, the patterned metal layer formed on the surface of the gate insulation layer comprises a storage capacitor line and a data line, and the storage capacitor line has a main portion and an extending portion substantially perpendicular to the main portion, wherein the main portion is substantially parallel to the data line and the extending portion is substantially parallel to the scan line; a flat layer covering over the substrate; and a pixel electrode disposed on the surface of the flat layer, which connects with the drain, and overlapping parts of the scan line, parts of the data line, parts of the storage capacitor fine, and parts of the extending portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for manufacturing an array substrate comprising the following steps:
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Providing a substrate; Forming a gate metal layer on the substrate, wherein the gate metal layer serves as a gate and a scan line; Forming a gate insulation layer on the substrate to covering the gate metal layer; Forming a semiconductor layer on the surface of the gate insulation layer corresponding to the gate; Forming a patterned metal layer on the surface of the semiconductor layer and the surface of the gate insulation layer, wherein the patterned metal layer formed on the surface of the semiconductor layer comprises a source and a drain, the patterned metal layer formed on the surface of the gate insulation layer comprises a storage capacitor line and a data line, wherein the storage capacitor has a main portion and an extending portion substantially perpendicular to the main portion, wherein the main portion is substantially parallel to the data line and the extending portion is substantially parallel to the scan line; Forming a patterned flat layer over the substrate to cover the patterned metal layer, the gate insulation layer, and the semiconductor layer; and Forming a pixel electrode on the surface of the flat layer to overlap parts of the scan line, parts of the data line, parts of the storage capacitor line and parts of the extending portion wherein the pixel electrode connects with the drain. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification