Elimination of gate oxide weak spot in deep trench

• US 8,115,252 B2
• Filed: 05/12/2005
• Issued: 02/14/2012
• Est. Priority Date: 05/12/2005
• Status: Expired due to Fees

• Current Assignee: M-Mos Sdn., Bhd., M-Mos Semiconductor Sdn. Bhd.
• Original Assignee: M-Mos Sdn., Bhd.
• Inventors: Hshieh, Fwu-Iuan, Keong, Ng Yeow, Fai, Yee Ai
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Kalam, Abul
• Application Number:
  US11/127,718
• Publication Number:
  US 20060255402A1
• Time in Patent Office: 2,469 Days
• Field of Search: 257330-334, 438/270, 438/271
• US Class Current: 257/333
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A MOSFET with a 0.7˜2.0 micrometers deep trench is formed by first carrying out a processing step of opening a trench in a semiconductor substrate. A thick insulator layer is then deposited in the trench such that the film at the bottom of the trench is much thicker than the sidewall of the trench. The insulator layer at the sidewall is then removed followed by the creation of composite dual layers that form the Gate Oxide. Another embodiment has the insulator layer deposited after Gate Oxide growth and stop at a thin Nitride layer which serves as stop layer during insulator pullback at trench sidewall and during Polysilicon CMP. Embodiments of the present invention eliminates weak spot at trench bottom corner encountered when Gate Oxide is grown in a 0.2 micrometers deep trench with thick bottom oxide. The present invention also maintains good control of the shape of the trench and the thickness profile of the Gate Oxide

Claims

1. A semiconductor power device supported on a semiconductor substrate comprising:

a trench gate of said semiconductor power device opened in said semiconductor substrate wherein a bottom surface and sidewalls of said trench gate are covered by a first and a second gate insulation layers wherein said second gate insulation layer covers entirely over said first gate insulation layer and constituting a single stop layer for covering and protecting said first gate insulation layer; and

a thick dielectric layer disposed at a bottom of said trench gate on top of and surrounded by the second gate insulation layer and said trench gate further comprises a polysilicon layer filling the trench gate on top of the thick dielectric layer wherein said second gate insulation layer covers and protects said first gate insulation layer in a wet etch process performed on said thick dielectric layer.

2. The semiconductor power device of claim 1 wherein:

said first gate insulation layer comprising a thermally grown oxide layer covering over a bottom surface and lower bottom sidewalls of said trench gate.

3. The semiconductor power device of claim 1 wherein:

said trench gate is approximately 0.7 to 2.0 micrometers deep opened into said semiconductor substrate.

4. The semiconductor power device of claim 1 wherein:

said trench gate is less than 0.5 micrometers wide opened in said semiconductor substrate.

5. The semiconductor power device of claim 1 wherein:

said trench gate is approximately 0.7 to 2.0 micrometers deep opened into said semiconductor substrate and said thick dielectric layer has a thickness approximately between 0.1 to 0.3 micrometers.

6. The semiconductor power device of claim 1 wherein:

said first gate insulation layer comprising a thermally grown oxide layer of approximately 200 to 1000 Angstroms in thickness and said second gate insulation layer is composed of an etch stop material for entirely covering and protecting said first gate insulation layer.

7. The semiconductor power device of claim 1 wherein:

said second gate insulation layer comprising a silicon nitride layer covering said first gate insulation layer.

8. The semiconductor power device of claim 1 wherein:

said second gate insulation layer comprising a silicon oxynitride layer covering said first gate insulation layer.

9. The semiconductor power device of claim 1 wherein:

said thick dielectric layer disposed at said bottom of said trench further comprising a local oxidation of silicon (LOCOS) layer.

10. The semiconductor power device of claim 1 wherein:

said thick dielectric layer disposed at said bottom of said trench further comprising a local oxidation of silicon (LOCOS) surrounded by said first gate insulation layer comprising a thermally grown oxide layer covered over by said second gate insulation layer chemically deposited as a silicon nitride layer.

11. The semiconductor power device of claim 1 wherein:

said thick dielectric layer disposed at said bottom of said trench further comprising a thermally grown thick oxide layer surrounded by said first gate insulation layer covered over by said second gate insulation layer chemically deposited as a silicon nitride layer.

12. The semiconductor power device of claim 1 wherein:

said thick dielectric layer disposed at said bottom of said trench further comprising a deposited thick oxide layer surrounded by said second gate insulation layer chemically deposited as a silicon nitride layer over said first gate insulation layer.