Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same

• US 8,115,254 B2
• Filed: 09/25/2007
• Issued: 02/14/2012
• Est. Priority Date: 09/25/2007
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Zhu, Huilong, Greene, Brian J., Chidambarrao, Dureseti, Freeman, Gregory G.
• Primary Examiner(s): Warren, Matthew E
• Assistant Examiner(s): CHEN, DAVID Z
• Application Number:
  US11/860,851
• Publication Number:
  US 20090079026A1
• Time in Patent Office: 1,603 Days
• Field of Search: 257/510, 257/E21.546, 257/E21.561, 257/374, 257/E21.545, 257/E21.547, 257/E21.564, 257/395, 257/396, 257/397, 257/354, 257/347, 257/E29.295, 257/E27.111, 257/E27.112, 257/E29.02, 438/435, 438/436
• US Class Current: 257/347
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/1025 Channel region of field-effect devices
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/84 controllable by variation of applied mechanical force, e.g. of pressure

Abstract

A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

Claims

1. A semiconductor structure comprising:

a semiconductor-on-insulator (SOI) substrate including a handle substrate, at least one buried insulator portion located on a top surface of said handle substrate, and at least one top semiconductor portion located on a top surface of said at least one buried insulator portion;

a trench extending from a top surface of said at least one top semiconductor portion to a depth below said top surface of said at least one buried insulator portion; and

a stack of an insulator stressor plug and a silicon oxide plug located in said trench, wherein said insulator stressor plug has a bottom surface in direct contact with the handle substrate at a bottom surface of said trench and an upper surface of the insulator stressor plug is present between the top surface of the at least one top semiconductor portion and a lower surface of the at least one top semiconductor portion, and said silicon oxide plug has an upper surface spanning an entire width of the trench, wherein the upper surface of the silicon oxide plug is substantially coplanar with said top surface of said at least one top semiconductor portion, and wherein said silicon oxide plug has sidewalls in direct contact with sidewalls of said trench, and further wherein said insulator stressor plug and said silicon oxide plug are the only materials filling said trench.

2. The semiconductor structure of claim 1, wherein said insulator stressor plug comprises a silicon nitride and applies a tensile stress or a compressive stress to said at least one top semiconductor portion.

3. The semiconductor structure of claim 2, wherein a magnitude of said tensile stress or said compressive stress is greater than 0.2 GPa in a region in said at least one top semiconductor portion.

4. The semiconductor structure of claim 1, wherein said insulator stressor plug laterally abuts, and encloses, said at least one buried insulator portion.

5. The semiconductor structure of claim 4, wherein said insulator stressor plug laterally abuts and encloses said at least one top semiconductor portion.

6. The semiconductor structure of claim 1, wherein said at least one top semiconductor portion comprises one of silicon, germanium, a silicon germanium alloy, a silicon carbon alloy, and a silicon germanium carbon alloy.

7. The semiconductor structure of claim 1, wherein a thickness of said at least one top semiconductor portion is from about 5 nm to about 300 nm, and wherein a depth of said trench is from about 200 nm to about 8,000 nm.

8. A method of forming a semiconductor structure comprising:

forming a trench extending from a top surface of a semiconductor-on-insulator (SOI) substrate to a depth beneath a bottom surface of a buried insulator layer of said SOI substrate, wherein the semiconductor-on-insulator substrate includes at least one top semiconductor portion on the buried insulator layer, wherein the buried insulator layer is present on a handle substrate; and

forming a stack of an insulator stressor plug and a silicon oxide plug in said trench, wherein said insulator stressor plug has a bottom surface in direct contact with the handle substrate at a bottom surface of said trench, and an upper surface of the insulator stressor plug is present between a top surface of the at least one top semiconductor portion and a lower surface of the at least one top semiconductor portion, and wherein said silicon oxide plug has an upper surface spanning an entire width of the trench, wherein the upper surface of the silicon oxide plug is substantially coplanar with the top surface of the at least one top semiconductor portion, and wherein said silicon oxide plug has sidewalls that are in direct contact with sidewalls of said trench, and further wherein said insulator stressor plug and said silicon oxide plug are the only materials filling said trench.

9. The method of claim 8, further comprising:

forming a stack of pad layers directly on said SOT substrate;

applying a photoresist on said stack of pad layers and lithographically patterning said photoresist; and

transferring a pattern in said photoresist into said stack of pad layers and said SOI substrate by at least one reactive etch.

10. The method of claim 8, wherein said trench laterally abuts and encloses said at least one top semiconductor portion and at least one portion of the buried insulator layer, wherein said at least one portion of the buried insulator layer vertically abuts said at least one top semiconductor portion.

11. The method of claim 8, further comprising:

depositing a silicon nitride layer into said trench; and

recessing said silicon nitride layer in said trench to form said insulator stressor plug.

12. The method of claim 11, wherein said insulator stressor plug comprises said silicon nitride layer and applies a compressive stress or a tensile stress to said at least one top semiconductor portion.

13. The method of claim 12, wherein a magnitude of said tensile stress or said compressive stress exceeds 0.2 GPa in a region in said at least one top semiconductor portion.

14. The method of claim 11, further comprising:

depositing a silicon oxide layer into said trench on top of said insulator stressor plug; and

recessing said silicon oxide layer in said trench to form said silicon oxide plug.

15. The method of claim 14, wherein a thickness of said at least one top semiconductor portion is from about 5 nm to about 300 nm, and wherein a depth of said trench is from about 200 nm to about 8,000 nm.